On Fri, Sep 7, 2018 at 3:34 PM, Alan Swanson <rei...@improbability.net> wrote:
> On Fri, 2018-09-07 at 15:01 -0400, Marek Olšák wrote:
>> On Fri, Sep 7, 2018 at 11:04 AM, Michel Dänzer <mic...@daenzer.net>
>> wrote:
>> > On 2018-09-07 4:31 p.m., Marek Olšák wrote:
>> > >
>> > > I don't think the performance can be worse than it is right now.
>> >
>> > In the worst case, all processes using OpenGL (or at least their
>> > OpenGL
>> > related threads, but that usually includes the main thread) could
>> > end up
>> > restricted to the same 4 cores, leaving up to 28 cores underused.
>>
>> 4C/4T used to be a standard and certainly enough for gaming. 4C/8T
>> used to be luxury before Ryzen, which is now the CCX. We should be
>> fine with 4 cores.
>
> So, for Ryzen processors where the CCX core split is 2+2 (1400/1500) or
> 3+3 (1600/2600) would you not be potentially overloading each CCX
> (regardless of SMT)?
>
> Otherwise, isn't a significant issue the CCX interconnect being
> hamstrung by being linked to memory speed and if you have fast memory
> (2933+) it's not such a burden?
There is no difference in performance for piglit/drawoverhead when
pinning all threads to only 2C/4T. This is how to do it:
index 751443f06f9..6da593b1d01 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -384,7 +384,7 @@ get_cpu_topology(void)
unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
if (cache_level == 3)
- util_cpu_caps.cores_per_L3 = cores_per_cache;
+ util_cpu_caps.cores_per_L3 = 4;
}
#endif
}
I don't know if fast memory would make any difference, but it can't be
faster than L3.
Marek
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