--- src/amd/common/ac_nir_to_llvm.c | 12 ++++++++---- src/compiler/glsl/glsl_to_nir.cpp | 2 +- src/compiler/nir/nir_builder.h | 12 ++++++++++++ src/compiler/spirv/vtn_glsl450.c | 4 ++-- .../drivers/freedreno/ir3/ir3_compiler_nir.c | 11 +++++++---- src/gallium/drivers/vc4/vc4_program.c | 8 ++++---- src/intel/compiler/brw_fs_nir.cpp | 19 ++++++++++++------- src/intel/compiler/brw_vec4_nir.cpp | 9 +++++---- src/mesa/program/prog_to_nir.c | 4 ++-- 9 files changed, 53 insertions(+), 28 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index c950b81dca2..d74a470db22 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -940,16 +940,20 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) src[1] = ac_to_integer(&ctx->ac, src[1]); result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]); break; - case nir_op_b2f: + case nir_op_b2f16: + case nir_op_b2f32: + case nir_op_b2f64: result = emit_b2f(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size); break; - case nir_op_f2b: + case nir_op_f2b32: result = emit_f2b(&ctx->ac, src[0]); break; - case nir_op_b2i: + case nir_op_b2i16: + case nir_op_b2i32: + case nir_op_b2i64: result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size); break; - case nir_op_i2b: + case nir_op_i2b32: src[0] = ac_to_integer(&ctx->ac, src[0]); result = emit_i2b(&ctx->ac, src[0]); break; diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 0479f8fcfe4..08ed01a3f6c 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -1516,7 +1516,7 @@ nir_visitor::visit(ir_expression *ir) result = supports_ints ? nir_u2f32(&b, srcs[0]) : nir_fmov(&b, srcs[0]); break; case ir_unop_b2f: - result = supports_ints ? nir_b2f(&b, srcs[0]) : nir_fmov(&b, srcs[0]); + result = supports_ints ? nir_b2f32(&b, srcs[0]) : nir_fmov(&b, srcs[0]); break; case ir_unop_f2i: case ir_unop_f2u: diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 3271a480520..d5bdc1568ae 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -825,6 +825,18 @@ nir_load_param(nir_builder *build, uint32_t param_idx) #include "nir_builder_opcodes.h" +static inline nir_ssa_def * +nir_f2b(nir_builder *build, nir_ssa_def *f) +{ + return nir_f2b32(build, f); +} + +static inline nir_ssa_def * +nir_i2b(nir_builder *build, nir_ssa_def *i) +{ + return nir_i2b32(build, i); +} + static inline nir_ssa_def * nir_load_barycentric(nir_builder *build, nir_intrinsic_op op, unsigned interp_mode) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 06a49e48e3f..b54aeb9b217 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@ -274,7 +274,7 @@ build_atan(nir_builder *b, nir_ssa_def *y_over_x) /* range-reduction fixup */ tmp = nir_fadd(b, tmp, nir_fmul(b, - nir_b2f(b, nir_flt(b, one, abs_y_over_x)), + nir_b2f32(b, nir_flt(b, one, abs_y_over_x)), nir_fadd(b, nir_fmul(b, tmp, nir_imm_float(b, -2.0f)), nir_imm_float(b, M_PI_2f)))); @@ -346,7 +346,7 @@ build_atan2(nir_builder *b, nir_ssa_def *y, nir_ssa_def *x) /* Calculate the arctangent and fix up the result if we had flipped the * coordinate system. */ - nir_ssa_def *arc = nir_fadd(b, nir_fmul(b, nir_b2f(b, flip), + nir_ssa_def *arc = nir_fadd(b, nir_fmul(b, nir_b2f32(b, flip), nir_imm_float(b, M_PI_2f)), build_atan(b, tan)); diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c index 0c7a722aa0c..41e819ab34f 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c @@ -1105,18 +1105,21 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) case nir_op_u2u8: dst[0] = create_cov(ctx, src[0], bs[0], alu->op); break; - case nir_op_f2b: + case nir_op_f2b32: dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_b2f: + case nir_op_b2f16: + case nir_op_b2f32: dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32); break; - case nir_op_b2i: + case nir_op_b2i8: + case nir_op_b2i16: + case nir_op_b2i32: dst[0] = ir3_b2n(b, src[0]); break; - case nir_op_i2b: + case nir_op_i2b32: dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index bc9bd76ae95..b4f6a5ecb50 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -1208,14 +1208,14 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) case nir_op_u2f32: result = qir_ITOF(c, src[0]); break; - case nir_op_b2f: + case nir_op_b2f32: result = qir_AND(c, src[0], qir_uniform_f(c, 1.0)); break; - case nir_op_b2i: + case nir_op_b2i32: result = qir_AND(c, src[0], qir_uniform_ui(c, 1)); break; - case nir_op_i2b: - case nir_op_f2b: + case nir_op_i2b32: + case nir_op_f2b32: qir_SF(c, src[0]); result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, qir_uniform_ui(c, ~0), diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2b36171136e..63426c2138d 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -787,8 +787,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_b2i: - case nir_op_b2f: + case nir_op_b2i8: + case nir_op_b2i16: + case nir_op_b2i32: + case nir_op_b2i64: + case nir_op_b2f16: + case nir_op_b2f32: + case nir_op_b2f64: op[0].type = BRW_REGISTER_TYPE_D; op[0].negate = !op[0].negate; /* fallthrough */ @@ -1212,15 +1217,15 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_i2b: - case nir_op_f2b: { + case nir_op_i2b32: + case nir_op_f2b32: { uint32_t bit_size = nir_src_bit_size(instr->src[0].src); if (bit_size == 64) { /* two-argument instructions can't take 64-bit immediates */ fs_reg zero; fs_reg tmp; - if (instr->op == nir_op_f2b) { + if (instr->op == nir_op_f2b32) { zero = vgrf(glsl_type::double_type); tmp = vgrf(glsl_type::double_type); bld.MOV(zero, setup_imm_df(bld, 0.0)); @@ -1239,10 +1244,10 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) } else { fs_reg zero; if (bit_size == 32) { - zero = instr->op == nir_op_f2b ? brw_imm_f(0.0f) : brw_imm_d(0); + zero = instr->op == nir_op_f2b32 ? brw_imm_f(0.0f) : brw_imm_d(0); } else { assert(bit_size == 16); - zero = instr->op == nir_op_f2b ? + zero = instr->op == nir_op_f2b32 ? retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF) : brw_imm_w(0); } bld.CMP(result, op[0], zero, BRW_CONDITIONAL_NZ); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 564be7e5eee..969f608c774 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1538,8 +1538,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) emit(AND(dst, op[0], op[1])); break; - case nir_op_b2i: - case nir_op_b2f: + case nir_op_b2i32: + case nir_op_b2f32: + case nir_op_b2f64: if (nir_dest_bit_size(instr->dest.dest) > 32) { assert(dst.type == BRW_REGISTER_TYPE_DF); emit_conversion_to_double(dst, negate(op[0]), false); @@ -1548,7 +1549,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } break; - case nir_op_f2b: + case nir_op_f2b32: if (nir_src_bit_size(instr->src[0].src) == 64) { /* We use a MOV with conditional_mod to check if the provided value is * 0.0. We want this to flush denormalized numbers to zero, so we set a @@ -1569,7 +1570,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } break; - case nir_op_i2b: + case nir_op_i2b32: emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ)); break; diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c index 47103306ad4..ee7d7d8f6d2 100644 --- a/src/mesa/program/prog_to_nir.c +++ b/src/mesa/program/prog_to_nir.c @@ -393,7 +393,7 @@ static void ptn_slt(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src) { if (b->shader->options->native_integers) { - ptn_move_dest(b, dest, nir_b2f(b, nir_flt(b, src[0], src[1]))); + ptn_move_dest(b, dest, nir_b2f32(b, nir_flt(b, src[0], src[1]))); } else { ptn_move_dest(b, dest, nir_slt(b, src[0], src[1])); } @@ -406,7 +406,7 @@ static void ptn_sge(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src) { if (b->shader->options->native_integers) { - ptn_move_dest(b, dest, nir_b2f(b, nir_fge(b, src[0], src[1]))); + ptn_move_dest(b, dest, nir_b2f32(b, nir_fge(b, src[0], src[1]))); } else { ptn_move_dest(b, dest, nir_sge(b, src[0], src[1])); } -- 2.19.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev