From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index dd6c56600b7..3fc1da8b0b8 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -450,26 +450,36 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct
amdgpu_winsys *ws,
if (r) {
fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
fprintf(stderr, "amdgpu: size : %"PRIu64" bytes\n", size);
fprintf(stderr, "amdgpu: alignment : %u bytes\n", alignment);
fprintf(stderr, "amdgpu: domains : %u\n", initial_domain);
goto error_bo_alloc;
}
va_gap_size = ws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0;
- unsigned vm_alignment = alignment;
+ uint64_t vm_alignment = alignment;
/* Increase the VM alignment for faster address translation. */
if (size >= ws->info.pte_fragment_size)
vm_alignment = MAX2(vm_alignment, ws->info.pte_fragment_size);
+ /* Gfx9: Increase the VM alignment to the most significant bit set
+ * in the size for faster address translation.
+ */
+ if (ws->info.chip_class >= GFX9) {
+ unsigned msb = util_last_bit64(size); /* 0 = no bit is set */
+ uint64_t msb_alignment = msb ? 1ull << (msb - 1) : 0;
+
+ vm_alignment = MAX2(vm_alignment, msb_alignment);
+ }
+
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
size + va_gap_size, vm_alignment, 0, &va,
&va_handle,
(flags & RADEON_FLAG_32BIT ?
AMDGPU_VA_RANGE_32_BIT : 0) |
AMDGPU_VA_RANGE_HIGH);
if (r)
goto error_va_alloc;
unsigned vm_flags = AMDGPU_VM_PAGE_READABLE |
AMDGPU_VM_PAGE_EXECUTABLE;
--
2.17.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
