From: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/amd/common/ac_debug.c | 2 ++ src/amd/common/sid.h | 1 + src/gallium/drivers/radeonsi/si_build_pm4.h | 8 +++++++- src/gallium/drivers/radeonsi/si_state_draw.c | 12 ++++++++---- 4 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c index 3b15398a2a2..e5463b66616 100644 --- a/src/amd/common/ac_debug.c +++ b/src/amd/common/ac_debug.c @@ -226,39 +226,41 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib, for (i = 0; i < ARRAY_SIZE(packet3_table); i++) if (packet3_table[i].op == op) break; if (i < ARRAY_SIZE(packet3_table)) { const char *name = sid_strings + packet3_table[i].name_offset; if (op == PKT3_SET_CONTEXT_REG || op == PKT3_SET_CONFIG_REG || op == PKT3_SET_UCONFIG_REG || + op == PKT3_SET_UCONFIG_REG_INDEX || op == PKT3_SET_SH_REG) fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n", name, predicate); else fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n", name, predicate); } else fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n", op, predicate); /* Print the contents. */ switch (op) { case PKT3_SET_CONTEXT_REG: ac_parse_set_reg_packet(f, count, SI_CONTEXT_REG_OFFSET, ib); break; case PKT3_SET_CONFIG_REG: ac_parse_set_reg_packet(f, count, SI_CONFIG_REG_OFFSET, ib); break; case PKT3_SET_UCONFIG_REG: + case PKT3_SET_UCONFIG_REG_INDEX: ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib); break; case PKT3_SET_SH_REG: ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib); break; case PKT3_ACQUIRE_MEM: ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); ac_dump_reg(f, ib->chip_class, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0); ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0); diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index a6d0bc2fe42..94709b486d0 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -204,20 +204,21 @@ /* fix CP DMA before uncommenting: */ /*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */ #define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */ #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */ #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */ #define PKT3_SET_CONFIG_REG 0x68 #define PKT3_SET_CONTEXT_REG 0x69 #define PKT3_SET_SH_REG 0x76 #define PKT3_SET_SH_REG_OFFSET 0x77 #define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */ +#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */ #define PKT3_LOAD_CONST_RAM 0x80 #define PKT3_WRITE_CONST_RAM 0x81 #define PKT3_DUMP_CONST_RAM 0x83 #define PKT3_INCREMENT_CE_COUNTER 0x84 #define PKT3_INCREMENT_DE_COUNTER 0x85 #define PKT3_WAIT_ON_CE_COUNTER 0x86 #define PKT3_LOAD_CONTEXT_REG 0x9F /* new for VI */ #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30) #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index 796adda0963..4e8890a5f97 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -93,26 +93,32 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); } static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_uconfig_reg_seq(cs, reg, 1); radeon_emit(cs, value); } static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, + struct si_screen *screen, unsigned reg, unsigned idx, unsigned value) { assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); assert(cs->current.cdw + 3 <= cs->current.max_dw); - radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); + assert(idx != 0); + unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX; + if (screen->info.chip_class < GFX9 || + (screen->info.chip_class == GFX9 && screen->info.me_fw_version < 26)) + opcode = PKT3_SET_UCONFIG_REG; + radeon_emit(cs, PKT3(opcode, 1, 0)); radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); radeon_emit(cs, value); } /* Emit PKT3_SET_CONTEXT_REG if the register value is different. */ static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset, enum si_tracked_reg reg, unsigned value) { struct radeon_cmdbuf *cs = sctx->gfx_cs; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 254f9edeb75..d011adb2cad 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -611,31 +611,34 @@ static void si_emit_draw_registers(struct si_context *sctx, { struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned prim = si_conv_pipe_prim(info->mode); unsigned ia_multi_vgt_param; ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches); /* Draw state. */ if (ia_multi_vgt_param != sctx->last_multi_vgt_param) { if (sctx->chip_class >= GFX9) - radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param); + radeon_set_uconfig_reg_idx(cs, sctx->screen, + R_030960_IA_MULTI_VGT_PARAM, 4, + ia_multi_vgt_param); else if (sctx->chip_class >= CIK) radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); else radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); sctx->last_multi_vgt_param = ia_multi_vgt_param; } if (prim != sctx->last_prim) { if (sctx->chip_class >= CIK) - radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); + radeon_set_uconfig_reg_idx(cs, sctx->screen, + R_030908_VGT_PRIMITIVE_TYPE, 1, prim); else radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); sctx->last_prim = prim; } /* Primitive restart. */ if (info->primitive_restart != sctx->last_primitive_restart_en) { if (sctx->chip_class >= GFX9) radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, @@ -709,22 +712,23 @@ static void si_emit_draw_packets(struct si_context *sctx, index_type = V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN && sctx->chip_class <= CIK ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0); break; default: assert(!"unreachable"); return; } if (sctx->chip_class >= GFX9) { - radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE, - 2, index_type); + radeon_set_uconfig_reg_idx(cs, sctx->screen, + R_03090C_VGT_INDEX_TYPE, 2, + index_type); } else { radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); radeon_emit(cs, index_type); } sctx->last_index_size = index_size; } index_max_size = (indexbuf->width0 - index_offset) / index_size; -- 2.19.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev