3-src instructions don't support immediates, but since 36bc5f06dd22,
we allow them on MAD and LRP relying on the combine constants pass to
fix it up later. However, that pass is specialized for 32-bit float
immediates and can't handle HF constants at present, so this patch
ensures that copy-propagation only does this for 32-bit constants.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/intel/compiler/brw_fs_copy_propagation.cpp | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp
b/src/intel/compiler/brw_fs_copy_propagation.cpp
index a8ec1c34630..c01d4ec4a4f 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -762,8 +762,16 @@ fs_visitor::try_constant_propagate(fs_inst *inst,
acp_entry *entry)
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
- inst->src[i] = val;
- progress = true;
+ /* 3-src instructions can't take IMM registers, however, for 32-bit
+ * floating instructions we rely on the combine constants pass to fix
+ * it up. For anything else, we shouldn't be promoting immediates
+ * until we can make the pass capable of combining constants of
+ * different sizes.
+ */
+ if (val.type == BRW_REGISTER_TYPE_F) {
+ inst->src[i] = val;
+ progress = true;
+ }
break;
default:
--
2.17.1
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