On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim <dongwon....@intel.com> wrote: > > set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register Repacking
With minor nits fixed. This series is: Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> I'll push the series after testing with these changes. Thanks for the patches :) > if the gen attribute, 'disable_ccs_repack' is set. > > Signed-off-by: Dongwon Kim <dongwon....@intel.com> > --- > src/intel/vulkan/genX_state.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c > index 21b8cd648d4..c1163628cc0 100644 > --- a/src/intel/vulkan/genX_state.c > +++ b/src/intel/vulkan/genX_state.c > @@ -225,6 +225,24 @@ genX(init_device_state)(struct anv_device *device) > } > #endif > > +#if GEN_GEN >= 11 > + /* hardware specification recommends disabling repacking for > + * the compatibility with decompression mechanism in display controller. > + */ > + if (device->info.disable_ccs_repack) { > + uint32_t cache_mode_0; > + anv_pack_struct(&cache_mode_0, > + GENX(CACHE_MODE_0), > + .DisableRepackingforCompression = true, > + .DisableRepackingforCompressionMask = true); > + > + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { > + lri.RegisterOffset = GENX(CACHE_MODE_0_num); > + lri.DataDWord = cache_mode_0; > + } > + } > +#endif > + > /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so > * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address. > * > -- > 2.17.1 > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev