Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
On 7/18/19 2:51 AM, Dave Airlie wrote:
From: Dave Airlie <airl...@redhat.com> Enabling tracing, and then having a vmfault, can leads to a segfault before we print out the traces, as if a meta shader is executing and we don't have the NIR for it. Just pass the stage and give back a default. Fixes: 9b9ccee4d64 ("radv: take LDS into account for compute shader occupancy stats") --- src/amd/vulkan/radv_nir_to_llvm.c | 8 ++++++-- src/amd/vulkan/radv_private.h | 1 + src/amd/vulkan/radv_shader.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 3e18303879e..c08789a4361 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -4244,9 +4244,10 @@ ac_setup_rings(struct radv_shader_context *ctx)unsignedradv_nir_get_max_workgroup_size(enum chip_class chip_class, + gl_shader_stage stage, const struct nir_shader *nir) { - switch (nir->info.stage) { + switch (stage) { case MESA_SHADER_TESS_CTRL: return chip_class >= GFX7 ? 128 : 64; case MESA_SHADER_GEOMETRY: @@ -4257,6 +4258,8 @@ radv_nir_get_max_workgroup_size(enum chip_class chip_class, return 0; }+ if (!nir)+ return chip_class >= GFX9 ? 128 : 64; unsigned max_workgroup_size = nir->info.cs.local_size[0] * nir->info.cs.local_size[1] * nir->info.cs.local_size[2]; @@ -4340,7 +4343,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, for (int i = 0; i < shader_count; ++i) { ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size, radv_nir_get_max_workgroup_size(ctx.options->chip_class, - shaders[i])); + shaders[i]->info.stage, + shaders[i])); }if (ctx.ac.chip_class >= GFX10) {diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 931d4039397..f1f30887e01 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2138,6 +2138,7 @@ void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm, const struct radv_nir_compiler_options *options);unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,+ gl_shader_stage stage, const struct nir_shader *nir);/* radv_shader_info.h */diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index bcc050a86cc..8f24a6d72b0 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1232,7 +1232,7 @@ generate_shader_stats(struct radv_device *device, lds_increment); } else if (stage == MESA_SHADER_COMPUTE) { unsigned max_workgroup_size = - radv_nir_get_max_workgroup_size(chip_class, variant->nir); + radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir); lds_per_wave = (conf->lds_size * lds_increment) / DIV_ROUND_UP(max_workgroup_size, 64); }
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