Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
 src/amd/vulkan/radv_device.c | 34 +++++++++-------------------------
 1 file changed, 9 insertions(+), 25 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 15bda6822e8..6e313aa9aa1 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2158,7 +2158,6 @@ fill_geom_tess_rings(struct radv_queue *queue,
                   index stride 64 */
                desc[0] = esgs_va;
                desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
-                         S_008F04_STRIDE(0) |
                          S_008F04_SWIZZLE_ENABLE(true);
                desc[2] = esgs_ring_size;
                desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
@@ -2167,7 +2166,7 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
                          S_008F0C_ELEMENT_SIZE(1) |
                          S_008F0C_INDEX_STRIDE(3) |
-                         S_008F0C_ADD_TID_ENABLE(true);
+                         S_008F0C_ADD_TID_ENABLE(1);
 
                if (queue->device->physical_device->rad_info.chip_class >= 
GFX10) {
                        desc[3] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
@@ -2182,17 +2181,12 @@ fill_geom_tess_rings(struct radv_queue *queue,
                /* stride 0, num records - size, elsize0,
                   index stride 0 */
                desc[4] = esgs_va;
-               desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
-                         S_008F04_STRIDE(0) |
-                         S_008F04_SWIZZLE_ENABLE(false);
+               desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
                desc[6] = esgs_ring_size;
                desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_ELEMENT_SIZE(0) |
-                         S_008F0C_INDEX_STRIDE(0) |
-                         S_008F0C_ADD_TID_ENABLE(false);
+                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
 
                if (queue->device->physical_device->rad_info.chip_class >= 
GFX10) {
                        desc[7] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
@@ -2213,17 +2207,12 @@ fill_geom_tess_rings(struct radv_queue *queue,
                /* stride 0, num records - size, elsize0,
                   index stride 0 */
                desc[0] = gsvs_va;
-               desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
-                         S_008F04_STRIDE(0) |
-                         S_008F04_SWIZZLE_ENABLE(false);
+               desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
                desc[2] = gsvs_ring_size;
                desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_ELEMENT_SIZE(0) |
-                         S_008F0C_INDEX_STRIDE(0) |
-                         S_008F0C_ADD_TID_ENABLE(false);
+                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
 
                if (queue->device->physical_device->rad_info.chip_class >= 
GFX10) {
                        desc[3] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
@@ -2238,9 +2227,8 @@ fill_geom_tess_rings(struct radv_queue *queue,
                   elsize 4, index stride 16 */
                /* shader will patch stride and desc[2] */
                desc[4] = gsvs_va;
-               desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
-                         S_008F04_STRIDE(0) |
-                         S_008F04_SWIZZLE_ENABLE(true);
+               desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
+                         S_008F04_SWIZZLE_ENABLE(1);
                desc[6] = 0;
                desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
@@ -2268,9 +2256,7 @@ fill_geom_tess_rings(struct radv_queue *queue,
                uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
 
                desc[0] = tess_va;
-               desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
-                         S_008F04_STRIDE(0) |
-                         S_008F04_SWIZZLE_ENABLE(false);
+               desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
                desc[2] = tess_factor_ring_size;
                desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
@@ -2287,9 +2273,7 @@ fill_geom_tess_rings(struct radv_queue *queue,
                }
 
                desc[4] = tess_offchip_va;
-               desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
-                         S_008F04_STRIDE(0) |
-                         S_008F04_SWIZZLE_ENABLE(false);
+               desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
                desc[6] = tess_offchip_ring_size;
                desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
-- 
2.22.0

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