[Mesa-dev] [PATCH 5/5] r600g: split cayman common state out into a shared function

alexdeucher Thu, 25 Oct 2012 09:01:48 -0700

From: Alex Deucher <alexander.deuc...@amd.com>

And use it for compute.  This should improve compute support
on cayman.


Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 src/gallium/drivers/r600/evergreen_compute.c |    8 ++++-
 src/gallium/drivers/r600/evergreen_state.c   |   39 ++++++++++++++++---------
 src/gallium/drivers/r600/r600_pipe.h         |    4 ++
 3 files changed, 35 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 55906c9..1e1ed4a 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -681,8 +681,12 @@ void evergreen_init_atom_start_compute_cs(struct 
r600_context *ctx)
        }
 
        /* Config Registers */
-       evergreen_init_common_regs(cb, ctx->chip_class
-                       , ctx->family, ctx->screen->info.drm_minor);
+       if (ctx->chip_class < CAYMAN)
+               evergreen_init_common_regs(cb, ctx->chip_class, ctx->family,
+                                          ctx->screen->info.drm_minor);
+       else
+               cayman_init_common_regs(cb, ctx->chip_class, ctx->family,
+                                       ctx->screen->info.drm_minor);
 
        /* The primitive type always needs to be POINTLIST for compute. */
        r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE,
diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 1bf6996..96e246a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2427,6 +2427,29 @@ void evergreen_init_state_functions(struct r600_context 
*rctx)
        evergreen_init_compute_state_functions(rctx);
 }
 
+void cayman_init_common_regs(struct r600_command_buffer *cb,
+                            enum chip_class ctx_chip_class,
+                            enum radeon_family ctx_family,
+                            int ctx_drm_minor)
+{
+       r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
+       r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
+       /* always set the temp clauses */
+       r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* 
R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
+
+       r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 
2);
+       r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
+       r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
+
+       r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 
8));
+
+       r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
+
+       r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, 
S_028354_SURFACE_SYNC_MASK(0xf));
+
+       r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
+}
+
 static void cayman_init_atom_start_cs(struct r600_context *rctx)
 {
        struct r600_command_buffer *cb = &rctx->start_cs_cmd;
@@ -2442,18 +2465,8 @@ static void cayman_init_atom_start_cs(struct 
r600_context *rctx)
        r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
        r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | 
EVENT_INDEX(4));
 
-       r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
-       r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
-       /* always set the temp clauses */
-       r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* 
R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
-
-       r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 
2);
-       r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
-       r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
-
-       r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 
8));
-
-       r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
+       cayman_init_common_regs(cb, rctx->chip_class,
+                               rctx->family, rctx->screen->info.drm_minor);
 
        r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
        r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, 
S_00913C_VTX_DONE_DELAY(4));
@@ -2622,8 +2635,6 @@ static void cayman_init_atom_start_cs(struct r600_context 
*rctx)
        r600_store_value(cb, 0);
        r600_store_value(cb, 0);
 
-       r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, 
S_028354_SURFACE_SYNC_MASK(0xf));
-       r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
        if (rctx->screen->has_streamout) {
                r600_store_context_reg(cb, 
R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
        }
diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index 2690c1b..3474a59 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -512,6 +512,10 @@ void evergreen_init_common_regs(struct r600_command_buffer 
*cb,
                                enum chip_class ctx_chip_class,
                                enum radeon_family ctx_family,
                                int ctx_drm_minor);
+void cayman_init_common_regs(struct r600_command_buffer *cb,
+                            enum chip_class ctx_chip_class,
+                            enum radeon_family ctx_family,
+                            int ctx_drm_minor);
 
 void evergreen_init_state_functions(struct r600_context *rctx);
 void evergreen_init_atom_start_cs(struct r600_context *rctx);
-- 
1.7.7.5

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[Mesa-dev] [PATCH 5/5] r600g: split cayman common state out into a shared function

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