From: José Fonseca <jfons...@vmware.com> The ADDR file is cumbersome for native integer capable drivers. We should consider deprecating it eventually, but this just adds support for indirection from TEMP registers. --- src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c index 9caac21..bd783b5 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c @@ -533,9 +533,23 @@ get_indirect_index(struct lp_build_tgsi_soa_context *bld, base = lp_build_const_int_vec(bld->bld_base.base.gallivm, uint_bld->type, reg_index); assert(swizzle < 4); - rel = LLVMBuildLoad(builder, - bld->addr[indirect_reg->Index][swizzle], - "load addr reg"); + switch (indirect_reg->File) { + case TGSI_FILE_ADDRESS: + rel = LLVMBuildLoad(builder, + bld->addr[indirect_reg->Index][swizzle], + "load addr reg"); + /* ADDR registers are uint */ + break; + case TGSI_FILE_TEMPORARY: + rel = lp_get_temp_ptr_soa(bld, indirect_reg->Index, swizzle); + rel = LLVMBuildLoad(builder, rel, "load temp reg"); + /* TEMP registers are float type */ + rel = LLVMBuildBitCast(builder, rel, uint_bld->vec_type, ""); + break; + default: + assert(0); + rel = uint_bld->zero; + } index = lp_build_add(uint_bld, base, rel); -- 1.7.9.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev