On 02/13/2013 06:31 PM, Eric Anholt wrote:
Kenneth Graunke <kenn...@whitecape.org> writes:
Meta-instructions that implicitly write then read/consume a MRF value
don't pose write-after-write conflicts with each other, since they're
actually:
- Write value 1, then consume it.
- Write value 2, then consume it.
OK, here's the case I'm thinking of:
1: MOV m2, temp1
2: send m2 no_implied_write
3: send m2 implied_write_m2
4: send m2 implied_write_m2
5: MOV m2, temp2
6: send m2 no_implied_write
Before this series we had deps:
2 -> 1 (RAW)
3 -> 2 (WAW)
4 -> 3 (WAW)
5 -> 4 (WAW)
6 -> 5 (RAW)
I'm concerned that now you only have deps:
2 -> 1 (RAW)
3 -> 2 (WAW)
5 -> 4 (WAW)
5 -> 2 (RAW)
6 -> 5 (RAW)
and that now a possible ordering would be:
1: MOV m2, value
2: send m2 no_implied_write
4: send m2 implied_write_m2
5: MOV m2, value
3: send m2 implied_write_m2
6: send m2 no_implied_write
and "6: send" will be broken.
I could definitely have missed something -- this stuff is super twisty.
I double checked your work and got an extra 3 -> 1 (WAW) dependency, but
that doesn't matter. The reordering you mentioned is indeed possible.
Thanks.
Consider patches 1 & 2 NAK'd...I'm working on a new series...
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