From: Alex Deucher <alexander.deuc...@amd.com>
I don't see why we shouldn't be setting these bits on 6xx/7xx
as well. They shouldn't hurt anything and we may be missing
synchronizations with certain blocks by not setting them.
The ddx already sets cp_coher_cntl in a similar manner.
v2: adjust selected bits.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
src/gallium/drivers/r600/r600_hw_context.c | 12 +++++++++++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index cf72549..735fdf2 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -669,12 +669,22 @@ void r600_flush_emit(struct r600_context *rctx)
S_0085F0_SH_ACTION_ENA(1) |
S_0085F0_SMX_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
- } else {
+ } else if (rctx->chip_class == R700) {
cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
S_0085F0_SH_ACTION_ENA(1) |
S_0085F0_VC_ACTION_ENA(1) |
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
+ } else if (rctx->chip_class == R600) {
+ cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
+ S_0085F0_SH_ACTION_ENA(1) |
+ S_0085F0_VC_ACTION_ENA(1) |
+ S_0085F0_TC_ACTION_ENA(1) |
+ S_0085F0_FULL_CACHE_ENA(1) |
+ S_0085F0_CB0_DEST_BASE_ENA(1) |
+ S_0085F0_CB1_DEST_BASE_ENA(1) |
+ S_0085F0_CB_ACTION_ENA(1) |
+ S_0085F0_DEST_BASE_0_ENA(1);
}
emit_flush = 1;
}
--
1.7.7.5
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