Am 07.03.2013 17:05, schrieb Michel Dänzer:
From: Michel Dänzer <michel.daen...@amd.com>
This is certainly not the last word on scheduling for this target, but
right now this allows a few apps to run / finish with radeonsi, most
notably UT2004 / Lightsmark. They fail to compile some shaders with the
default scheduler because it ends up trying to spill registers, which
we don't support yet (and which is probably a bad idea in general for
performance if it can be avoided).
NOTE: This is a candidate for the Mesa stable branch.
Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
BTW: I played around with making the SMRD patterns trivial
rematerializable, that should reduce the register pressure for SGPRs
quite a bit. But unfortunately I couldn't find an use case where we run
out of SGPRs before running out of VGPRs. Just leave me a note (or the
shader code) if you got such a use case.
Christian.
---
lib/Target/R600/SIISelLowering.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index cc53488..b9cc09f 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -68,6 +68,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setTargetDAGCombine(ISD::SELECT_CC);
setTargetDAGCombine(ISD::SETCC);
+
+ setSchedulingPreference(Sched::Source);
}
SDValue SITargetLowering::LowerFormalArguments(
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