Am 30.07.2013 18:13, schrieb srol...@vmware.com: > From: Roland Scheidegger <srol...@vmware.com> > > Previously, nothing was said what happens with shift counts exceeding > bit width of the values to shift. In theory 3 behaviors are possible: > 1) undefined (classic c definition) > 2) just shift out all bits (so result is zero, or -1 potentially for ashr) > 3) mask the shift count to bit width - 1 > API's either require 3) or are ok with 1). In particular, GLSL (as well as a > couple uninteresting legacy GL extensions) is happy with undefined, whereas > both OpenCL and d3d10 require 3). Consequently, most hw also implements 3). > So, for simplicity we just specify that 3) is required rather than saying > undefined and then needing state trackers to work around it.
> Also while here specify shift count as a vector, not scalar. As far as I > can tell this was a doc bug, neither state trackers nor drivers used scalar > shift count. Hmm actually I'm no longer sure this was a simple doc bug. I notice that in fact d3d10 (but not d3d11!) requires a scalar shift count. Though glsl/EXT_gpu_shader4 say it works with both scalar and vector shift counts, and obviously while scalar shift count behavior can be implemented with vector shift count the opposite isn't true. So regardless if this was a doc bug or not, I still propose to change this, and it still seems drivers/state trackers didn't honor this anyway. Roland > --- > src/gallium/docs/source/tgsi.rst | 30 ++++++++++++++++++------------ > 1 file changed, 18 insertions(+), 12 deletions(-) > > diff --git a/src/gallium/docs/source/tgsi.rst > b/src/gallium/docs/source/tgsi.rst > index 0557ce0..8506b7e 100644 > --- a/src/gallium/docs/source/tgsi.rst > +++ b/src/gallium/docs/source/tgsi.rst > @@ -1254,41 +1254,47 @@ Support for these opcodes indicated by > PIPE_SHADER_CAP_INTEGERS (all of them?) > > .. opcode:: SHL - Shift Left > > + The shift count is masked with 0x1f before the shift is applied. > + > .. math:: > > - dst.x = src0.x << src1.x > + dst.x = src0.x << (0x1f & src1.x) > > - dst.y = src0.y << src1.x > + dst.y = src0.y << (0x1f & src1.y) > > - dst.z = src0.z << src1.x > + dst.z = src0.z << (0x1f & src1.z) > > - dst.w = src0.w << src1.x > + dst.w = src0.w << (0x1f & src1.w) > > > .. opcode:: ISHR - Arithmetic Shift Right (of Signed Integer) > > + The shift count is masked with 0x1f before the shift is applied. > + > .. math:: > > - dst.x = src0.x >> src1.x > + dst.x = src0.x >> (0x1f & src1.x) > > - dst.y = src0.y >> src1.x > + dst.y = src0.y >> (0x1f & src1.y) > > - dst.z = src0.z >> src1.x > + dst.z = src0.z >> (0x1f & src1.z) > > - dst.w = src0.w >> src1.x > + dst.w = src0.w >> (0x1f & src1.w) > > > .. opcode:: USHR - Logical Shift Right > > + The shift count is masked with 0x1f before the shift is applied. > + > .. math:: > > - dst.x = src0.x >> (unsigned) src1.x > + dst.x = src0.x >> (unsigned) (0x1f & src1.x) > > - dst.y = src0.y >> (unsigned) src1.x > + dst.y = src0.y >> (unsigned) (0x1f & src1.y) > > - dst.z = src0.z >> (unsigned) src1.x > + dst.z = src0.z >> (unsigned) (0x1f & src1.z) > > - dst.w = src0.w >> (unsigned) src1.x > + dst.w = src0.w >> (unsigned) (0x1f & src1.w) > > > .. opcode:: UCMP - Integer Conditional Move > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
