On 08/20/2013 11:30 AM, Paul Berry wrote: [snip]
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index ae4cab5..9053ea2 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -252,6 +252,12 @@ enum brw_urb_write_flags { BRW_URB_WRITE_COMPLETE = 0x8,/** + * Indicates that an additional offset (which may be different for the two + * vec4 slots) is stored in the message header (gen == 7). + */ + BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10, + + /** * Convenient combination of flags: end the thread while simultaneously * marking the given URB entry as complete. */ diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 622b22f..b55b57e 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -531,8 +531,8 @@ static void brw_set_urb_message( struct brw_compile *p, insn->bits3.urb_gen7.offset = offset; assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE); insn->bits3.urb_gen7.swizzle_control = swizzle_control; - /* per_slot_offset = 0 makes it ignore offsets in message header */ - insn->bits3.urb_gen7.per_slot_offset = 0; + insn->bits3.urb_gen7.per_slot_offset = + flags & BRW_URB_WRITE_PER_SLOT_OFFSET ? 1 : 0; insn->bits3.urb_gen7.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0; } else if (brw->gen >= 5) { insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */
I might split these out to a separate patch, as well, since this patch doesn't actually use them.
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