On 09/30/2013 12:35 PM, Ben Widawsky wrote:
> Starting with Ivybridge, the hierarchical had relaxed requirements for
> its allocation. Following a "simple" formula in the bspec was all you
> needed to satisfy the requirement.
>
> To prepare the code for this, extract all places where the miptree was
> used, when we really only needed the region. This allows an upcoming
> patch to simply allocate the region, and not the whole miptree.
>
> v2: Don't use intel_region. Instead use bo + stride. We actually do
> store the stride in libdrm, but it is inaccessible in the current
> libdrm version.
>
> CC: Chad Versace <chad.vers...@linux.intel.com>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
> src/mesa/drivers/dri/i965/brw_misc_state.c | 11 +++++---
> src/mesa/drivers/dri/i965/gen6_blorp.cpp | 20 +++++++++------
> src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 ++---
> src/mesa/drivers/dri/i965/gen7_misc_state.c | 5 ++--
> src/mesa/drivers/dri/i965/intel_fbo.c | 4 +--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36
> +++++++++++++++------------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++++-
> 7 files changed, 52 insertions(+), 36 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 7f4cd6f..23ffeab 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -210,8 +210,12 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
> *depth_mt,
> &tile_mask_x, &tile_mask_y, false);
>
> if (intel_miptree_slice_has_hiz(depth_mt, depth_level, depth_layer)) {
> + uint32_t tmp;
> uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
> - intel_region_get_tile_masks(depth_mt->hiz_mt->region,
> + struct intel_region region = { .cpp = depth_mt->cpp };
> +
> + drm_intel_bo_get_tiling(depth_mt->hiz_buffer.bo, ®ion.tiling, &tmp);
> + intel_region_get_tile_masks(®ion,
Mixing of tabs and spaces. I know the kernel likes tabs, but we're
trying to get rid of them in Mesa. All spaces, all the time.
> &hiz_tile_mask_x, &hiz_tile_mask_y,
> false);
>
> /* Each HiZ row represents 2 rows of pixels */
> @@ -667,11 +671,10 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
>
> /* Emit hiz buffer. */
> if (hiz) {
> - struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
> BEGIN_BATCH(3);
> OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> - OUT_BATCH(hiz_mt->region->pitch - 1);
> - OUT_RELOC(hiz_mt->region->bo,
> + OUT_BATCH(depth_mt->hiz_buffer.stride - 1);
> + OUT_RELOC(depth_mt->hiz_buffer.bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> brw->depthstencil.hiz_offset);
> ADVANCE_BATCH();
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> index da523e5..fc3a331 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -887,16 +887,22 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context
> *brw,
>
> /* 3DSTATE_HIER_DEPTH_BUFFER */
> {
> - struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
> - uint32_t hiz_offset =
> - intel_region_get_aligned_offset(hiz_region,
> - draw_x & ~tile_mask_x,
> - (draw_y & ~tile_mask_y) / 2, false);
> + uint32_t hiz_offset, tmp;
> + struct intel_mipmap_tree *depth_mt = params->depth.mt;
> + struct intel_region hiz_region;
> +
> + hiz_region.cpp = depth_mt->cpp;
> + hiz_region.pitch = depth_mt->hiz_buffer.stride;
> + drm_intel_bo_get_tiling(depth_mt->hiz_buffer.bo, &hiz_region.tiling,
> &tmp);
> +
> + hiz_offset = intel_region_get_aligned_offset(&hiz_region,
> + draw_x & ~tile_mask_x,
> + (draw_y & ~tile_mask_y) / 2,
> false);
>
> BEGIN_BATCH(3);
> OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> - OUT_BATCH(hiz_region->pitch - 1);
> - OUT_RELOC(hiz_region->bo,
> + OUT_BATCH(hiz_region.pitch - 1);
> + OUT_RELOC(depth_mt->hiz_buffer.bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> hiz_offset);
> ADVANCE_BATCH();
> diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> index 9df3d92..379e8ee 100644
> --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> @@ -737,13 +737,13 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context
> *brw,
>
> /* 3DSTATE_HIER_DEPTH_BUFFER */
> {
> - struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
> + struct intel_mipmap_tree *depth_mt = params->depth.mt;
>
> BEGIN_BATCH(3);
> OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> OUT_BATCH((mocs << 25) |
> - (hiz_region->pitch - 1));
> - OUT_RELOC(hiz_region->bo,
> + (depth_mt->hiz_buffer.stride - 1));
> + OUT_RELOC(depth_mt->hiz_buffer.bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> 0);
> ADVANCE_BATCH();
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> index eb942cf..cb0594d 100644
> --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> @@ -143,12 +143,11 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> OUT_BATCH(0);
> ADVANCE_BATCH();
> } else {
> - struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
> BEGIN_BATCH(3);
> OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
> OUT_BATCH((mocs << 25) |
> - (hiz_mt->region->pitch - 1));
> - OUT_RELOC(hiz_mt->region->bo,
> + (depth_mt->hiz_buffer.stride - 1));
> + OUT_RELOC(depth_mt->hiz_buffer.bo,
> I915_GEM_DOMAIN_RENDER,
> I915_GEM_DOMAIN_RENDER,
> 0);
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 1692325..4ce205f 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -452,9 +452,9 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
>
> intel_renderbuffer_set_draw_offset(irb);
>
> - if (mt->hiz_mt == NULL && brw_is_hiz_depth_format(brw, rb->Format)) {
> + if (mt->hiz_buffer.bo == NULL && brw_is_hiz_depth_format(brw,
> rb->Format)) {
> intel_miptree_alloc_hiz(brw, mt);
> - if (!mt->hiz_mt)
> + if (!mt->hiz_buffer.bo)
> return false;
> }
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 2f5e04f..e1da9de 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -793,7 +793,8 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
>
> intel_region_release(&((*mt)->region));
> intel_miptree_release(&(*mt)->stencil_mt);
> - intel_miptree_release(&(*mt)->hiz_mt);
> + intel_miptree_release(&(*mt)->hiz_buffer.mt);
> + (*mt)->hiz_buffer.bo = NULL;
> intel_miptree_release(&(*mt)->mcs_mt);
> intel_miptree_release(&(*mt)->singlesample_mt);
> intel_resolve_map_clear(&(*mt)->hiz_map);
> @@ -1250,7 +1251,7 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw,
> uint32_t level,
> uint32_t layer)
> {
> - assert(mt->hiz_mt);
> + assert(mt->hiz_buffer.bo);
>
> if (brw->is_haswell) {
> const struct intel_mipmap_level *l = &mt->level[level];
> @@ -1276,22 +1277,25 @@ bool
> intel_miptree_alloc_hiz(struct brw_context *brw,
> struct intel_mipmap_tree *mt)
> {
> - assert(mt->hiz_mt == NULL);
> - mt->hiz_mt = intel_miptree_create(brw,
> - mt->target,
> - mt->format,
> - mt->first_level,
> - mt->last_level,
> - mt->logical_width0,
> - mt->logical_height0,
> - mt->logical_depth0,
> - true,
> - mt->num_samples,
> - INTEL_MIPTREE_TILING_ANY);
> -
> - if (!mt->hiz_mt)
> + assert(mt->hiz_buffer.mt == NULL);
> + mt->hiz_buffer.mt = intel_miptree_create(brw,
> + mt->target,
> + mt->format,
> + mt->first_level,
> + mt->last_level,
> + mt->logical_width0,
> + mt->logical_height0,
> + mt->logical_depth0,
> + true,
> + mt->num_samples,
> + INTEL_MIPTREE_TILING_ANY);
> +
> + if (!mt->hiz_buffer.mt)
> return false;
>
> + mt->hiz_buffer.bo = mt->hiz_buffer.mt->region->bo;
> + mt->hiz_buffer.stride = mt->hiz_buffer.mt->region->pitch;
> +
> /* Mark that all slices need a HiZ resolve. */
> struct intel_resolve_map *head = &mt->hiz_map;
> for (int level = mt->first_level; level <= mt->last_level; ++level) {
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index d718125..92d26fa 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -414,7 +414,11 @@ struct intel_mipmap_tree
> * To determine if hiz is enabled, do not check this pointer. Instead, use
> * intel_miptree_slice_has_hiz().
> */
> - struct intel_mipmap_tree *hiz_mt;
> + struct {
> + struct intel_mipmap_tree *mt;
> + drm_intel_bo *bo;
> + uint32_t stride;
> + } hiz_buffer;
>
> /**
> * \brief Map of miptree slices to needed resolves.
>
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