Bspec: "Prior to changing the Surface State Base Address, the resouce streamer must be disabled within a batch buffer where the RS is enabled. RS is re-enabled again once the SBA is updated."
The resource streamer can be toggled within a batch using MI_RS_CONTROL. Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com> --- src/mesa/drivers/dri/i965/brw_misc_state.c | 7 +++++++ src/mesa/drivers/dri/i965/brw_state.h | 3 +++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 6 ++++++ src/mesa/drivers/dri/i965/gen7_misc_state.c | 8 ++++++++ 4 files changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 7f4cd6f..5ee2bbc 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -977,6 +977,9 @@ static void upload_state_base_address( struct brw_context *brw ) if (brw->gen == 6) intel_emit_post_sync_nonzero_flush(brw); + if (brw->has_resource_streamer) + gen7_rs_control(brw, 0x0); + BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */ @@ -1014,6 +1017,10 @@ static void upload_state_base_address( struct brw_context *brw ) OUT_BATCH(1); /* Indirect object upper bound */ OUT_BATCH(1); /* Instruction access upper bound */ ADVANCE_BATCH(); + + if (brw->has_resource_streamer) + gen7_rs_control(brw, 0x1); + } else if (brw->gen == 5) { BEGIN_BATCH(8); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index ec64328..144d370 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -252,6 +252,9 @@ gen7_upload_constant_state(struct brw_context *brw, const struct brw_stage_state *stage_state, bool active, unsigned opcode); +/* gen7_misc_state.c */ +void gen7_rs_control(struct brw_context *brw, int enable); + #ifdef __cplusplus } #endif diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index da523e5..e77b6fb 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -74,6 +74,9 @@ gen6_blorp_emit_state_base_address(struct brw_context *brw, { uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0; + if (brw->has_resource_streamer) + gen7_rs_control(brw, 0x0); + BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */ @@ -102,6 +105,9 @@ gen6_blorp_emit_state_base_address(struct brw_context *brw, OUT_BATCH(1); /* IndirectObjectUpperBound*/ OUT_BATCH(1); /* InstructionAccessUpperBound */ ADVANCE_BATCH(); + + if (brw->has_resource_streamer) + gen7_rs_control(brw, 0x1); } diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index eb942cf..60ba484 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -203,3 +203,11 @@ const struct brw_tracked_state gen7_depthbuffer = { }, .emit = brw_emit_depthbuffer, }; + +void +gen7_rs_control(struct brw_context *brw, int enable) +{ + BEGIN_BATCH(1); + OUT_BATCH(MI_RS_CONTROL | enable); + ADVANCE_BATCH(); +} -- 1.7.9.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev