Re: [Mesa-dev] [PATCH 1/2] r600/uvd: fix mapping of UVD surfaces for readback

[Grigori Goronzy]

On 10.10.2013 11:41, Christian König wrote:
Am 09.10.2013 22:19, schrieb Grigori Goronzy:
R600_RESOURCE_FLAG_TRANSFER forces direct mapping, and reading from
VRAM is simply too slow. VDPAU GetBitsYCbCr is unusuable. Change to
the new PIPE_BIND_LINEAR and adjust r600_transfer_map so that it uses
a staging texture.

Looks good on the first glance.

Please split the patch into two, with the first one making the required
changes to r600_texture.c and the second with the changes to r600_uvd.c.
Also please provide a third patch replacing R600_RESOURCE_FLAG_TRANSFER
with PIPE_BIND_LINEAR in radeonsi_uvd.c as well.


Will do. I am also experimenting with making UVD tiling work, but I 
really think we should be able to map linear surfaces efficiently.

Grigori

Christian.

---
  src/gallium/drivers/r600/r600_uvd.c       | 6 +++---
  src/gallium/drivers/radeon/r600_texture.c | 6 ++++++
  2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_uvd.c
b/src/gallium/drivers/r600/r600_uvd.c
index 05d2ad0..300bccb 100644
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -77,7 +77,7 @@ struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context *pipe,

      vl_video_buffer_template(&templ, &template, resource_formats[0],
1, array_size, PIPE_USAGE_STATIC, 0);
      if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced)
-        templ.flags = R600_RESOURCE_FLAG_TRANSFER;
+        templ.bind = PIPE_BIND_LINEAR;
      resources[0] = (struct r600_texture *)
          pipe->screen->resource_create(pipe->screen, &templ);
      if (!resources[0])
@@ -86,7 +86,7 @@ struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context *pipe,
      if (resource_formats[1] != PIPE_FORMAT_NONE) {
          vl_video_buffer_template(&templ, &template,
resource_formats[1], 1, array_size, PIPE_USAGE_STATIC, 1);
          if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced)
-            templ.flags = R600_RESOURCE_FLAG_TRANSFER;
+            templ.bind = PIPE_BIND_LINEAR;
          resources[1] = (struct r600_texture *)
              pipe->screen->resource_create(pipe->screen, &templ);
          if (!resources[1])
@@ -96,7 +96,7 @@ struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context *pipe,
      if (resource_formats[2] != PIPE_FORMAT_NONE) {
          vl_video_buffer_template(&templ, &template,
resource_formats[2], 1, array_size, PIPE_USAGE_STATIC, 2);
          if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced)
-            templ.flags = R600_RESOURCE_FLAG_TRANSFER;
+            templ.bind = PIPE_BIND_LINEAR;
          resources[2] = (struct r600_texture *)
              pipe->screen->resource_create(pipe->screen, &templ);
          if (!resources[2])
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index ebb70906..2ab174a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -852,6 +852,12 @@ static void *r600_texture_transfer_map(struct
pipe_context *ctx,
      if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
          use_staging_texture = TRUE;

+    /* Untiled buffers likely in VRAM, which is slow for CPU reads */
+    if ((usage & PIPE_TRANSFER_READ) && !(usage &
PIPE_TRANSFER_MAP_DIRECTLY) &&
+        (texture->usage & PIPE_USAGE_STATIC)) {
+        use_staging_texture = TRUE;
+    }
+
      /* Use a staging texture for uploads if the underlying BO is
busy. */
      if (!(usage & PIPE_TRANSFER_READ) &&
          (r600_rings_is_buffer_referenced(rctx,
rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||

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