From: Marek Olšák <marek.ol...@amd.com>
The DMA functions modify dst_offset and size and util_range_add gets wrong
values.
---
src/gallium/drivers/r600/evergreen_hw_context.c | 18 ++++++++++++------
src/gallium/drivers/r600/r600_hw_context.c | 18 ++++++++++++------
src/gallium/drivers/radeonsi/si_descriptors.c | 21 ++++++++++++---------
3 files changed, 36 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index e5d6249..85fdc4e 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -40,6 +40,12 @@ void evergreen_dma_copy(struct r600_context *rctx,
struct r600_resource *rdst = (struct r600_resource*)dst;
struct r600_resource *rsrc = (struct r600_resource*)src;
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&rdst->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
/* make sure that the dma ring is only one active */
rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
@@ -71,9 +77,6 @@ void evergreen_dma_copy(struct r600_context *rctx,
src_offset += csize << shift;
size -= csize;
}
-
- util_range_add(&rdst->valid_buffer_range, dst_offset,
- dst_offset + size);
}
/* The max number of bytes to copy per packet. */
@@ -88,6 +91,12 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
assert(size);
assert(rctx->screen->b.has_cp_dma);
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
+ offset + size);
+
offset += r600_resource_va(&rctx->screen->b.b, dst);
/* Flush the cache where the resource is bound. */
@@ -141,8 +150,5 @@ void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx,
rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
R600_CONTEXT_INV_VERTEX_CACHE |
R600_CONTEXT_INV_TEX_CACHE;
-
- util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
- offset + size);
}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 11414cb..da90d63 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -447,6 +447,12 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
assert(size);
assert(rctx->screen->b.has_cp_dma);
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
src_offset += r600_resource_va(&rctx->screen->b.b, src);
@@ -506,9 +512,6 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
R600_CONTEXT_INV_VERTEX_CACHE |
R600_CONTEXT_INV_TEX_CACHE;
-
- util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
- dst_offset + size);
}
void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
@@ -533,6 +536,12 @@ void r600_dma_copy(struct r600_context *rctx,
struct r600_resource *rdst = (struct r600_resource*)dst;
struct r600_resource *rsrc = (struct r600_resource*)src;
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&rdst->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
/* make sure that the dma ring is only one active */
rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -555,7 +564,4 @@ void r600_dma_copy(struct r600_context *rctx,
src_offset += csize << shift;
size -= csize;
}
-
- util_range_add(&rdst->valid_buffer_range, dst_offset,
- dst_offset + size);
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index e6d566d..c43b35e 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -659,6 +659,12 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
if (!size)
return;
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
+ offset + size);
+
/* Fallback for unaligned clears. */
if (offset % 4 != 0 || size % 4 != 0) {
uint32_t *map =
rctx->b.ws->buffer_map(r600_resource(dst)->cs_buf,
@@ -667,9 +673,6 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
size /= 4;
for (unsigned i = 0; i < size; i++)
*map++ = value;
-
- util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
- offset + size);
return;
}
@@ -723,9 +726,6 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB_META;
-
- util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
- offset + size);
}
void si_copy_buffer(struct r600_context *rctx,
@@ -735,6 +735,12 @@ void si_copy_buffer(struct r600_context *rctx,
if (!size)
return;
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
src_offset += r600_resource_va(&rctx->screen->b.b, src);
@@ -781,9 +787,6 @@ void si_copy_buffer(struct r600_context *rctx,
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB_META;
-
- util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
- dst_offset + size);
}
/* INIT/DEINIT */
--
1.8.3.2
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