Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits. So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 159f928..128eed9 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -178,6 +178,11 @@ void intel_batchbuffer_cached_advance(struct brw_context
*brw);
read_domains, write_domain, delta); \
} while (0)
+/* Handle 48-bit address relocations for Gen8+ */
+#define OUT_RELOC64(buf, read_domains, write_domain, delta) \
+ OUT_RELOC(buf, read_domains, write_domain, delta); \
+ OUT_BATCH(0);
+
#define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
#define CACHED_BATCH() intel_batchbuffer_cached_advance(brw);
--
1.8.4.4
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