This fixes framebuffer_blit_functionality_scissor_blit.test in gles3 cts. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/gen8_depth_state.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index 8c70c62..7f1c23d 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -30,6 +30,17 @@ #include "brw_defines.h" /** + * The documentation for Broadwell's Hierarchical Depth Buffer Resolve and for + * Depth Buffer Clear mandates the rectangle to be 8x4 aligned. + */ +static void +align_rectangle_primitive(uint32_t *width, uint32_t *height) +{ + *width = ALIGN(*width, 8); + *height = ALIGN(*height, 4); +} + +/** * Helper function to emit depth related command packets. */ static void @@ -54,6 +65,8 @@ emit_depth_packets(struct brw_context *brw, return; } + align_rectangle_primitive(&width, &height); + intel_emit_depth_stall_flushes(brw); /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */ @@ -248,6 +261,8 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, unsigned rect_width = minify(mt->logical_width0, level); unsigned rect_height = minify(mt->logical_height0, level); + align_rectangle_primitive(&rect_width, &rect_height); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); OUT_BATCH(0); -- 1.9.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev