On Thu, Aug 7, 2014 at 4:06 PM, Alex Deucher <alexdeuc...@gmail.com> wrote: > On Wed, Aug 6, 2014 at 5:49 PM, Marek Olšák <mar...@gmail.com> wrote: >> From: Marek Olšák <marek.ol...@amd.com> >> >> R600-R700 don't support virtual memory. > > For consistency, it might be nice to use gpu_address here as well, but > just set it to 0 for 6xx/7xx. Either way, series is:
Well, r600_resource_va isn't used elsewhere in the file. These are only a few cases that seem to have been copied from the same evergreen code. I assumed somebody had forgotten to clean them up. Marek > Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> > >> --- >> src/gallium/drivers/r600/r600_state.c | 27 +++++++++------------------ >> 1 file changed, 9 insertions(+), 18 deletions(-) >> >> diff --git a/src/gallium/drivers/r600/r600_state.c >> b/src/gallium/drivers/r600/r600_state.c >> index 258ffd1..607b199 100644 >> --- a/src/gallium/drivers/r600/r600_state.c >> +++ b/src/gallium/drivers/r600/r600_state.c >> @@ -595,25 +595,22 @@ texture_buffer_sampler_view(struct >> r600_pipe_sampler_view *view, >> unsigned width0, unsigned height0) >> >> { >> - struct pipe_context *ctx = view->base.context; >> struct r600_texture *tmp = (struct r600_texture*)view->base.texture; >> - uint64_t va; >> int stride = util_format_get_blocksize(view->base.format); >> unsigned format, num_format, format_comp, endian; >> - unsigned offset = view->base.u.buf.first_element * stride; >> + uint64_t offset = view->base.u.buf.first_element * stride; >> unsigned size = (view->base.u.buf.last_element - >> view->base.u.buf.first_element + 1) * stride; >> >> r600_vertex_data_type(view->base.format, >> &format, &num_format, &format_comp, >> &endian); >> >> - va = r600_resource_va(ctx->screen, view->base.texture) + offset; >> view->tex_resource = &tmp->resource; >> - >> view->skip_mip_address_reloc = true; >> - view->tex_resource_words[0] = va; >> + >> + view->tex_resource_words[0] = offset; >> view->tex_resource_words[1] = size - 1; >> - view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) | >> + view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> >> 32UL) | >> S_038008_STRIDE(stride) | >> S_038008_DATA_FORMAT(format) | >> S_038008_NUM_FORMAT_ALL(num_format) | >> @@ -1105,8 +1102,7 @@ static void r600_init_depth_surface(struct >> r600_context *rctx, >> >> /* use htile only for first level */ >> if (rtex->htile_buffer && !level) { >> - uint64_t va = r600_resource_va(&rctx->screen->b.b, >> &rtex->htile_buffer->b.b); >> - surf->db_htile_data_base = va >> 8; >> + surf->db_htile_data_base = 0; >> surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | >> S_028D24_HTILE_HEIGHT(1) | >> S_028D24_FULL_CACHE(1) | >> @@ -1944,7 +1940,6 @@ static void r600_emit_shader_stages(struct >> r600_context *rctx, struct r600_atom >> >> static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom >> *a) >> { >> - struct pipe_screen *screen = rctx->b.b.screen; >> struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; >> struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; >> struct r600_resource *rbuffer; >> @@ -1955,8 +1950,7 @@ static void r600_emit_gs_rings(struct r600_context >> *rctx, struct r600_atom *a) >> >> if (state->enable) { >> rbuffer =(struct r600_resource*)state->esgs_ring.buffer; >> - r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, >> - (r600_resource_va(screen, &rbuffer->b.b)) >> >> 8); >> + r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); >> radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); >> radeon_emit(cs, r600_context_bo_reloc(&rctx->b, >> &rctx->b.rings.gfx, rbuffer, >> RADEON_USAGE_READWRITE, >> @@ -1965,8 +1959,7 @@ static void r600_emit_gs_rings(struct r600_context >> *rctx, struct r600_atom *a) >> state->esgs_ring.buffer_size >> 8); >> >> rbuffer =(struct r600_resource*)state->gsvs_ring.buffer; >> - r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, >> - (r600_resource_va(screen, &rbuffer->b.b)) >> >> 8); >> + r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); >> radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); >> radeon_emit(cs, r600_context_bo_reloc(&rctx->b, >> &rctx->b.rings.gfx, rbuffer, >> RADEON_USAGE_READWRITE, >> @@ -2644,8 +2637,7 @@ void r600_update_gs_state(struct pipe_context *ctx, >> struct r600_pipe_shader *sha >> r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS, >> S_02887C_NUM_GPRS(rshader->bc.ngpr) | >> S_02887C_STACK_SIZE(rshader->bc.nstack)); >> - r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, >> - r600_resource_va(ctx->screen, (void >> *)shader->bo) >> 8); >> + r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0); >> /* After that, the NOP relocation packet must be emitted >> (shader->bo, RADEON_USAGE_READ). */ >> } >> >> @@ -2659,8 +2651,7 @@ void r600_update_es_state(struct pipe_context *ctx, >> struct r600_pipe_shader *sha >> r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES, >> S_028890_NUM_GPRS(rshader->bc.ngpr) | >> S_028890_STACK_SIZE(rshader->bc.nstack)); >> - r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, >> - r600_resource_va(ctx->screen, (void >> *)shader->bo) >> 8); >> + r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0); >> /* After that, the NOP relocation packet must be emitted >> (shader->bo, RADEON_USAGE_READ). */ >> } >> >> -- >> 1.9.1 >> >> _______________________________________________ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev