On Thu, Aug 28, 2014 at 4:57 AM, Christian König
<[email protected]> wrote:
> Am 28.08.2014 um 08:56 schrieb Michel Dänzer:
>
>> From: Michel Dänzer <[email protected]>
>>
>> This flag is a hint that userspace expects the BO to be accessed by the
>> CPU. We can use that hint to prevent such BOs from ever being stored in
>> the CPU inaccessible part of VRAM.
>>
>> Signed-off-by: Michel Dänzer <[email protected]>
>
>
> This patch is Reviewed-by: Christian König <[email protected]>
Applied to my -next tree.
>
> I think we need a similar negative flags as well, e.g.
> RADEON_GEM_NO_CPU_ACCESS.
>
> This way we can stop forcing buffers into the visible VRAM while pinning
> them for scanout.
How about the attached patch?
Alex
>
> Regards,
> Christian.
>
>
>> ---
>> drivers/gpu/drm/radeon/radeon_object.c | 11 +++++++++--
>> include/uapi/drm/radeon_drm.h | 2 ++
>> 2 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_object.c
>> b/drivers/gpu/drm/radeon/radeon_object.c
>> index dc74cc5..908ea541 100644
>> --- a/drivers/gpu/drm/radeon/radeon_object.c
>> +++ b/drivers/gpu/drm/radeon/radeon_object.c
>> @@ -143,7 +143,12 @@ void radeon_ttm_placement_from_domain(struct
>> radeon_bo *rbo, u32 domain)
>> for (i = 0; i < c; ++i) {
>> rbo->placements[i].fpfn = 0;
>> - rbo->placements[i].lpfn = 0;
>> + if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
>> + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
>> + rbo->placements[i].lpfn =
>> + rbo->rdev->mc.visible_vram_size >>
>> PAGE_SHIFT;
>> + else
>> + rbo->placements[i].lpfn = 0;
>> }
>> /*
>> @@ -151,7 +156,9 @@ void radeon_ttm_placement_from_domain(struct radeon_bo
>> *rbo, u32 domain)
>> * improve fragmentation quality.
>> * 512kb was measured as the most optimal number.
>> */
>> - if (rbo->tbo.mem.size > 512 * 1024) {
>> + if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
>> + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
>> + rbo->tbo.mem.size > 512 * 1024) {
>> for (i = 0; i < c; i++) {
>> rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
>> }
>> diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
>> index 509b2d7..bf0067b 100644
>> --- a/include/uapi/drm/radeon_drm.h
>> +++ b/include/uapi/drm/radeon_drm.h
>> @@ -799,6 +799,8 @@ struct drm_radeon_gem_info {
>> #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
>> #define RADEON_GEM_GTT_UC (1 << 1)
>> #define RADEON_GEM_GTT_WC (1 << 2)
>> +/* BO is expected to be accessed by the CPU */
>> +#define RADEON_GEM_CPU_ACCESS (1 << 3)
>> struct drm_radeon_gem_create {
>> uint64_t size;
>
>
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From d6a65c62241fe2b3c1a0dd799f2af0802297446c Mon Sep 17 00:00:00 2001
From: Alex Deucher <[email protected]>
Date: Thu, 28 Aug 2014 10:59:05 -0400
Subject: [PATCH] drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag
Allows pinning of buffers in the non-CPU visible portion of
vram.
Signed-off-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/radeon/radeon_object.c | 10 +++++++---
include/uapi/drm/radeon_drm.h | 2 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 09b039a..b71e8e0 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -314,10 +314,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
unsigned lpfn = 0;
/* force to pin into visible video ram */
- if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
- lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
- else
+ if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) {
+ if (bo->flags & RADEON_GEM_NO_CPU_ACCESS)
+ lpfn = bo->rdev->mc.real_vram_size >> PAGE_SHIFT;
+ else
+ lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+ } else {
lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
+ }
if (max_offset)
lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index f755f20..d2346fd 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -803,6 +803,8 @@ struct drm_radeon_gem_info {
#define RADEON_GEM_GTT_WC (1 << 2)
/* BO is expected to be accessed by the CPU */
#define RADEON_GEM_CPU_ACCESS (1 << 3)
+/* BO is expected to not be accessed by the CPU */
+#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create {
uint64_t size;
--
1.8.3.1
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