On Thu, Feb 5, 2015 at 11:47 PM, Ian Romanick <i...@freedesktop.org> wrote:
>> diff --git a/src/glsl/ir.h b/src/glsl/ir.h
>> index a0f48b2..6e7c654 100644
>> --- a/src/glsl/ir.h
>> +++ b/src/glsl/ir.h
>> @@ -1275,6 +1275,13 @@ enum ir_expression_operation {
>> ir_unop_bitcast_f2u, /**< Bit-identical float-to-uint "conversion" */
>> ir_unop_any,
>>
>> + ir_unop_d2f, /**< Double-to-float conversion. */
>> + ir_unop_f2d, /**< Float-to-double conversion. */
>> + ir_unop_d2i, /**< Double-to-integer conversion. */
>> + ir_unop_i2d, /**< Integer-to-double conversion. */
>> + ir_unop_d2u, /**< Double-to-unsigned conversion. */
>> + ir_unop_u2d, /**< Unsigned-to-double conversion. */
>> +
>
> These should be properly ordered with the other cast operations. Also,
> ir_unop_d2b is missing.
I had the same comment elsewhere. Apparently they're just doing d2b
with d2f+f2b.
I guess that'll just work?
>> /**
>> * \name Unary floating-point rounding operations.
>> */
>> @@ -1345,6 +1352,17 @@ enum ir_expression_operation {
>> /*@}*/
>>
>> ir_unop_saturate,
>
> Blank line here.
>
>> + /**
>> + * \name Double packing, part of ARB_gpu_shader_fp64.
>> + */
>> + /*@{*/
>> + ir_unop_pack_double_2x32,
>> + ir_unop_unpack_double_2x32,
>> + /*@}*/
>> +
>> + ir_unop_frexp_sig,
>> + ir_unop_frexp_exp,
>
> I'm confused about these... what is it?
Split opcodes for the significand and exponent values output by frexp.
IIRC Dave was doing this so that radeon could in theory peephole them
back together into a two-output frexp instruction.
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