On Wed, Feb 11, 2015 at 05:08:33AM -0800, Kenneth Graunke wrote: > On Tuesday, February 10, 2015 05:22:45 PM Ben Widawsky wrote: > > Since we can be in this code with SIMD4x2, the execsize will be 4, and so > > the > > register width must be <= 4. If you use a vec8, the width is 8, and we'll > > assert > > fail. > > NAK with this rationale. > > brw_fs*.cpp is _only_ for SIMD8 (or SIMD16) mode. > > brw_vec4*cpp is for SIMD4x1/SIMD4x2 code. > > Code in brw_fs_generator.cpp absolutely cannot run in SIMD4x2 mode. >
I don't quite understand how the code works, but according to the comments in the code (which you reviewed) we take this path on SKL. See fs_visitor::lower_uniform_pull_constant_loads and fs_generator::generate_uniform_pull_constant_load_gen7 In either event, the patch fixes the aforementioned assertion - if you have a better explanation and/or fix, I would be happy to adjust. > > > > Fixes the following piglit tests: > > spec/glsl-1.20/compiler/structure-and-array-operations/array-selection.vert > > spec/glsl-es-3.00/compiler/uniform_block/interface-name-basic.vert > > spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-struct.vert > > spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-function.vert > > spec/glsl-es-3.00/compiler/uniform_block/interface-name-array.vert > > glslparsertest/glsl2/condition-07.vert > > spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert > > > > Cc: Neil Roberts <n...@linux.intel.com> > > Signed-off-by: Ben Widawsky <b...@bwidawsk.net> > > --- > > src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > > b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > > index 8cd36f8..f7b8771 100644 > > --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > > +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > > @@ -1024,13 +1024,13 @@ > > fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, > > > > if (brw->gen >= 9) { > > /* Skylake requires a message header in order to use SIMD4x2 mode. */ > > - src = retype(brw_vec8_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); > > + src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); > > mlen = 2; > > header_present = true; > > > > brw_push_insn_state(p); > > brw_set_default_mask_control(p, BRW_MASK_DISABLE); > > - brw_MOV(p, src, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); > > + brw_MOV(p, src, retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD)); > > brw_set_default_access_mode(p, BRW_ALIGN_1); > > > > brw_MOV(p, get_element_ud(src, 2), > > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev