On Thu, Feb 19, 2015 at 11:25:56PM -0800, Jordan Justen wrote: > On 2015-02-19 21:40:37, Ben Widawsky wrote: > > On Thu, Feb 19, 2015 at 03:42:05PM -0800, Jordan Justen wrote: > > > For fragment programs, we pull this mask from the payload header. The same > > > mask doesn't exist for compute shaders, so we set all bits to enabled. > > > > > > Note: this mask is ANDed with the execution mask, so some channels may > > > not end > > > up issuing the atomic operation. > > > > > > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > > > Cc: Ben Widawsky <b...@bwidawsk.net> > > > Cc: Francisco Jerez <curroje...@riseup.net> > > > > Just add to the commit message that this is needed specifically because > > compute > > is invoked as SIMD16 (and perhaps reference the other commits?) and it's: > > Reviewed-by: Ben Widawsky <b...@bwidawsk.net> > > Good idea. I'll add those. > > > Sorry it advance... > > we may as well just go for 0xffffffff in case we ever support SIMD32. > > I had been setting all 32-bits previously. I mentioned to you that I > thought this was needed for SIMD32. I wanted to double check it before > sending the patch out. I think I found the field for IVB in the PRM: > > IVB Vol 4 Part 1 3.9.9.9 Message Header > Pixel/Sample Mask > > ...and it looks like it is only 16-bits. Maybe Francisco can confirm > that I got it right. > > I couldn't find this same information in the HSW PRMs. > > I'm not sure what that means for SIMD32. > > -Jordan
I suspect it's because the docs are super suck wrt SIMD32... but if you looked and see nothing, just leave it be. Whomever enables SIMD32 can deal with it :-) [snip] > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
