The brw_imm_ud will yield a HW_REG which then will introduce a barrier
for certain optimization opportunities.
No piglit regressions seen with gen8 (simd8vs).
Suggested-by: Matt Turner <matts...@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Matt Turner <matts...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index fa7d32c..b1b75821 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -3016,7 +3016,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op,
unsigned surf_index,
*/
assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- brw_imm_ud(0xffff)))->force_writemask_all = true;
+ fs_reg(0xffff)))->force_writemask_all = true;
}
length++;
@@ -3079,7 +3079,7 @@ fs_visitor::emit_untyped_surface_read(unsigned
surf_index, fs_reg dst,
*/
assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- brw_imm_ud(0xffff)))->force_writemask_all = true;
+ fs_reg(0xffff)))->force_writemask_all = true;
}
/* Set the surface read offset. */
--
2.1.4
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