On Sat, Feb 28, 2015 at 12:27:05AM -0800, Kenneth Graunke wrote: > On Friday, February 27, 2015 10:22:11 AM Ben Widawsky wrote: > > Signed-off-by: Ben Widawsky <b...@bwidawsk.net> > > --- > > src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c > > b/src/mesa/drivers/dri/i965/intel_batchbuffer.c > > index b0ebec7..e405918 100644 > > --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c > > +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c > > @@ -32,6 +32,7 @@ > > #include "intel_buffers.h" > > #include "intel_fbo.h" > > #include "brw_context.h" > > +#include "brw_defines.h" > > > > static void > > intel_batchbuffer_reset(struct brw_context *brw); > > @@ -231,6 +232,21 @@ brw_finish_batch(struct brw_context *brw) > > if (brw->batch.ring == RENDER_RING) > > brw_perf_monitor_finish_batch(brw); > > > > + if (brw->is_haswell) { > > This appears to be listed as WaAvoidRCZCounterRollover in the > "Workarounds" docs page. The text there is slightly different: > > "Send CC_STATE_POINTERS command with cc modify enable set to true followed > by a PIPE_CONTROL with an RC flush at the end of every batch buffer > (also includes pre-empted batch buffers) where a depth read/write may > have occurred." > > Clearly, this only applies to render ring batches (as you can't put > 3DSTATE_CC_POINTERS in BLT batches anyway) - plus, those are the only > ones that do depth operations, plus, it says "3D batch buffer". > > So, you should put this code in the > > if (brw->batch.ring == RENDER_RING) > > block above. This will eliminate the need for patch 3 as well. >
Same here - sorry for wasting your time. I had fixed this too. If you have some time, see my workarounds branch: http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=workarounds I'll send it out after I get some piglit results. Thanks for finding the name of the workaround, I didn't see it anywhere. > > + /* SW must program 3DSTATE_CC_STATE_POINTERS command at the end of > > every > > + * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS > > stall. > > + * > > + * From the example in the docs, it seems to expect a regular pipe > > control > > + * flush here as well. We may have done it already, but meh. > > + */ > > + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); > > + BEGIN_BATCH(2); > > + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); > > + OUT_BATCH(brw->cc.state_offset | 1); > > + ADVANCE_BATCH(); > > + intel_batchbuffer_emit_mi_flush(brw); > > + } > > + > > /* Mark that the current program cache BO has been used by the GPU. > > * It will be reallocated if we need to put new programs in for the > > * next batch. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev