brw_imm_ud(0xffff) should have been converted to fs_reg(0xffffu) to make sure the uint32_t fs_reg constructor was matched.
commit 49a938a265f5959c9b558995cc658f80acb6eb18 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Fri Feb 20 12:12:25 2015 -0800 i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 57c4d66..51a1e03 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -3113,7 +3113,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, */ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - fs_reg(0xffff)))->force_writemask_all = true; + fs_reg(0xffffu)))->force_writemask_all = true; } length++; @@ -3176,7 +3176,7 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, */ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - fs_reg(0xffff)))->force_writemask_all = true; + fs_reg(0xffffu)))->force_writemask_all = true; } /* Set the surface read offset. */ -- 2.1.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev