From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_buffer_common.c | 6 ++++--
src/gallium/drivers/radeon/r600_pipe_common.c | 4 +++-
src/gallium/drivers/radeon/r600_texture.c | 8 +++++---
src/gallium/drivers/radeonsi/si_pipe.c | 4 +++-
src/gallium/drivers/radeonsi/si_state.c | 8 ++++----
5 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index fc5f6c2..ac395fa 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -121,7 +121,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
- if (rscreen->info.drm_minor < 40) {
+ if (rscreen->info.drm_major == 2 &&
+ rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
flags |= RADEON_FLAG_GTT_WC;
break;
@@ -147,7 +148,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
* Write-combined CPU mappings are fine, the kernel ensures all
CPU
* writes finish before the GPU executes a command stream.
*/
- if (rscreen->info.drm_minor < 40)
+ if (rscreen->info.drm_major == 2 &&
+ rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
else if (res->domains & RADEON_DOMAIN_VRAM)
flags |= RADEON_FLAG_CPU_ACCESS;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index c6d7918..3b26dea 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -864,7 +864,9 @@ bool r600_common_screen_init(struct r600_common_screen
*rscreen,
util_format_s3tc_init();
pipe_mutex_init(rscreen->aux_context_lock);
- if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags &
DBG_TRACE_CS)) {
+ if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
+ rscreen->info.drm_major == 3) &&
+ (rscreen->debug_flags & DBG_TRACE_CS)) {
rscreen->trace_bo = (struct
r600_resource*)pipe_buffer_create(&rscreen->b,
PIPE_BIND_CUSTOM,
PIPE_USAGE_STAGING,
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index dc510c9..1b64507 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -489,7 +489,7 @@ static unsigned r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
unsigned num_pipes = rscreen->tiling_info.num_channels;
if (rscreen->chip_class <= EVERGREEN &&
- rscreen->info.drm_minor < 26)
+ rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
return 0;
/* HW bug on R6xx. */
@@ -501,7 +501,7 @@ static unsigned r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rscreen->info.drm_minor < 38)
+ rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
return 0;
switch (num_pipes) {
@@ -1262,7 +1262,9 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
/* fast color clear with 1D tiling doesn't work on old kernels
and CIK */
if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rctx->chip_class >= CIK && rctx->screen->info.drm_minor <
38) {
+ rctx->chip_class >= CIK &&
+ rctx->screen->info.drm_major == 2 &&
+ rctx->screen->info.drm_minor < 38) {
continue;
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index e68c30e..91b4d6f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -259,7 +259,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return sscreen->b.chip_class < CIK ||
- sscreen->b.info.drm_minor >= 35;
+ (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor >= 35) ||
+ sscreen->b.info.drm_major == 3;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return R600_MAP_BUFFER_ALIGNMENT;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 7f0fdd5..eae5e6f 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1146,7 +1146,9 @@ static uint32_t si_translate_texformat(struct pipe_screen
*screen,
int first_non_void)
{
struct si_screen *sscreen = (struct si_screen*)screen;
- bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
+ bool enable_s3tc = (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor >= 31) ||
+ sscreen->b.info.drm_major == 3;
boolean uniform = TRUE;
int i;
@@ -1595,7 +1597,6 @@ boolean si_is_format_supported(struct pipe_screen *screen,
unsigned sample_count,
unsigned usage)
{
- struct si_screen *sscreen = (struct si_screen *)screen;
unsigned retval = 0;
if (target >= PIPE_MAX_TEXTURE_TYPES) {
@@ -1607,8 +1608,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
return FALSE;
if (sample_count > 1) {
- /* 2D tiling on CIK is supported since DRM 2.35.0 */
- if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor <
35)
+ if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
return FALSE;
switch (sample_count) {
--
2.1.0
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