On Thu, Apr 23, 2015 at 04:50:00PM -0700, Ben Widawsky wrote: > AFAICT, none of the old data was wrong (the gen7 decoder), but it wa smissing > a > bunch of stuff. > > Adds a tick (') to denote the beginning of the surface state for easier > reading. > This will be replaced later with some better, but more risky code. > > OLD: > 0x00007980: 0x23016000: SURF: 2D BRW_SURFACEFORMAT_B8G8R8A8_UNORM > 0x00007984: 0x18000000: SURF: offset > 0x00007988: 0x00ff00ff: SURF: 256x256 size, 0 mips, 1 slices > 0x0000798c: 0x000003ff: SURF: pitch 1024, tiled > 0x00007990: 0x00000000: SURF: min array element 0, array extent 1 > 0x00007994: 0x00000000: SURF: mip base 0 > 0x00007998: 0x00000000: SURF: x,y offset: 0,0 > 0x0000799c: 0x09770000: SURF: > 0x00007940: 0x231d7000: SURF: 2D BRW_SURFACEFORMAT_R8G8B8A8_UNORM > 0x00007944: 0x78000000: SURF: offset > 0x00007948: 0x001f001f: SURF: 32x32 size, 0 mips, 1 slices > 0x0000794c: 0x0000007f: SURF: pitch 128, tiled > 0x00007950: 0x00000000: SURF: min array element 0, array extent 1 > 0x00007954: 0x00000000: SURF: mip base 0 > 0x00007958: 0x00000000: SURF: x,y offset: 0,0 > 0x0000795c: 0x09770000: SURF: > > NEW: > 0x00007980: 0x23016000: SURF': 2D B8G8R8A8_UNORM VALIGN4 HALIGN4 > X-tiled > 0x00007984: 0x18000000: SURF: MOCS: 0x18 Base MIP: 0.0 (0 mips) > Surface QPitch: 0 > 0x00007988: 0x00ff00ff: SURF: 256x256 [AUX_NONE] > 0x0000798c: 0x000003ff: SURF: 1 slices (depth), pitch: 1024 > 0x00007990: 0x00000000: SURF: min array element: 0, array extent 1, > MULTISAMPLE_1 > 0x00007994: 0x00000000: SURF: x,y offset: 0,0, min LOD: 0 > 0x00007998: 0x00000000: SURF: AUX pitch: 0 qpitch: 0 > 0x0000799c: 0x09770000: SURF: Clear color: ---- > 0x00007940: 0x231d7000: SURF': 2D R8G8B8A8_UNORM VALIGN4 HALIGN4 > Y-tiled > 0x00007944: 0x78000000: SURF: MOCS: 0x78 Base MIP: 0 (0 mips) > Surface QPitch: ff0000 > 0x00007948: 0x001f001f: SURF: 32x32 [AUX_NONE] > 0x0000794c: 0x0000007f: SURF: 1 slices (depth), pitch: 128 > 0x00007950: 0x00000000: SURF: min array element: 0, array extent 1, > MULTISAMPLE_1 > 0x00007954: 0x00000000: SURF: x,y offset: 0,0, min LOD: 0 > 0x00007958: 0x00000000: SURF: AUX pitch: 0 qpitch: 0 > 0x0000795c: 0x09770000: SURF: Clear color: ---- > 0x00007920: 0x00007980: BIND0: surface state address > 0x00007924: 0x00007940: BIND1: surface state address > > Signed-off-by: Ben Widawsky <b...@bwidawsk.net> > --- > src/mesa/drivers/dri/i965/brw_defines.h | 4 +- > src/mesa/drivers/dri/i965/brw_state_dump.c | 86 > ++++++++++++++++++++++++++++-- > 2 files changed, 85 insertions(+), 5 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h > b/src/mesa/drivers/dri/i965/brw_defines.h > index e37d2e0..b9aae29 100644 > --- a/src/mesa/drivers/dri/i965/brw_defines.h > +++ b/src/mesa/drivers/dri/i965/brw_defines.h > @@ -529,9 +529,11 @@ > #define GEN7_SURFACE_ARYSPC_FULL (0 << 10) > #define GEN7_SURFACE_ARYSPC_LOD0 (1 << 10) > > -/* Surface state DW0 */ > +/* Surface state DW1 */ > #define GEN8_SURFACE_MOCS_SHIFT 24 > #define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24) > +#define GEN8_SURFACE_QPITCH_SHIFT 0 > +#define GEN8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0) > > /* Surface state DW2 */ > #define BRW_SURFACE_HEIGHT_SHIFT 19 > diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c > b/src/mesa/drivers/dri/i965/brw_state_dump.c > index 21a3d8f..642bdc8 100644 > --- a/src/mesa/drivers/dri/i965/brw_state_dump.c > +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c > @@ -59,6 +59,22 @@ static const char *sampler_addr_mode[] = { > "HALF_BORDER" > }; > > +static const char *surface_tiling[] = { > + "LINEAR", > + "W-tiled", > + "X-tiled", > + "Y-tiled" > +}; > + > +static const char *surface_aux_mode[] = { > + "AUX_NONE", > + "AUX_MCS", > + "AUX_APPEND", > + "AUX_HIZ", > + "RSVD", > + "RSVD" > +}; > + > static void > batch_out(struct brw_context *brw, const char *name, uint32_t offset, > int index, char *fmt, ...) PRINTFLIKE(5, 6); > @@ -461,6 +477,66 @@ static void dump_gen7_surface_state(struct brw_context > *brw, uint32_t offset) > batch_out(brw, name, offset, 7, "\n"); > } > > +static float q_to_float(uint32_t data, int integer_end, int integer_start, > + int fractional_end, int fractional_start) > +{ > + /* Convert the number to floating point. */ > + float n = GET_BITS(data, integer_start, fractional_end); > + > + /* Multiple by 2^-n */ > + return n * pow(2, -(fractional_end - fractional_start + 1)); > +} > + > +static void dump_gen8_surface_state(struct brw_context *brw, uint32_t offset) > +{ > + const char *name = "SURF"; > + uint32_t *surf = brw->batch.bo->virtual + offset;
const > + > + batch_out(brw, "SURF'", offset, 0, "%s %s %s VALIGN%d HALIGN%d %s\n", > + get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)), > + get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)), > + (surf[0] & GEN7_SURFACE_IS_ARRAY) ? "array" : "", > + 1 << (GET_BITS(surf[0], 17, 16) + 1), /* VALIGN */ > + 1 << (GET_BITS(surf[0], 15, 14) + 1), /* HALIGN */ > + surface_tiling[GET_BITS(surf[0], 13, 12)] > + ); > + batch_out(brw, name, offset, 1, "MOCS: 0x%x Base MIP: %.1f (%u mips) > Surface QPitch: %d\n", > + GET_FIELD(surf[1], GEN8_SURFACE_MOCS), > + q_to_float(surf[1], 23, 20, 19, 19), > + surf[5] & INTEL_MASK(3, 0), > + GET_FIELD(surf[1], GEN8_SURFACE_QPITCH) << 2 > + ); > + batch_out(brw, name, offset, 2, "%dx%d [%s]\n", > + GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1, > + GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1, > + surface_aux_mode[surf[7] & INTEL_MASK(2, 0)] Shouldn't this be? surface_aux_mode[surf[6] & INTEL_MASK(2, 0)] With a fix or an explanation: Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > + ); > + batch_out(brw, name, offset, 3, "%d slices (depth), pitch: %d\n", > + GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1, > + (surf[3] & INTEL_MASK(17, 0)) + 1 > + ); > + batch_out(brw, name, offset, 4, "min array element: %d, array extent %d, > MULTISAMPLE_%d\n", > + GET_FIELD(surf[4], GEN7_SURFACE_MIN_ARRAY_ELEMENT), > + GET_FIELD(surf[4], GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT) + 1, > + 1 << GET_BITS(surf[4], 5, 3) > + ); > + batch_out(brw, name, offset, 5, "x,y offset: %d,%d, min LOD: %d\n", > + GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET), > + GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET), > + GET_FIELD(surf[5], GEN7_SURFACE_MIN_LOD) > + ); > + batch_out(brw, name, offset, 6, "AUX pitch: %d qpitch: %d\n", > + GET_FIELD(surf[6], GEN8_SURFACE_AUX_QPITCH) << 2, > + GET_FIELD(surf[6], GEN8_SURFACE_AUX_PITCH) << 2 > + ); > + batch_out(brw, name, offset, 7, "Clear color: %c%c%c%c\n", > + GET_BITS(surf[7], 31, 31) ? 'R' : '-', > + GET_BITS(surf[7], 30, 30) ? 'G' : '-', > + GET_BITS(surf[7], 29, 29) ? 'B' : '-', > + GET_BITS(surf[7], 28, 28) ? 'A' : '-' > + ); > +} > + > static void > dump_sdc(struct brw_context *brw, uint32_t offset) > { > @@ -843,11 +919,13 @@ dump_state_batch(struct brw_context *brw) > dump_binding_table(brw, offset, size); > break; > case AUB_TRACE_SURFACE_STATE: > - if (brw->gen < 7) { > - dump_surface_state(brw, offset); > - } else { > + if (brw->gen >= 8) { > + dump_gen8_surface_state(brw, offset); > + } else if (brw->gen >= 7) { > dump_gen7_surface_state(brw, offset); > - } > + } else { > + dump_surface_state(brw, offset); > + } > break; > case AUB_TRACE_SAMPLER_STATE: > if (brw->gen >= 7) > -- > 2.3.6 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev