From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/r600/r600_pipe.c | 3 +++
src/gallium/drivers/radeon/r600_pipe_common.c | 20 ++++++++++++++++++++
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 3 +++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 8 ++++++++
src/gallium/winsys/radeon/drm/radeon_winsys.h | 5 +++--
6 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 21e5d42..4b19c7f 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -270,6 +270,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
return 1;
+ case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
+ return rscreen->b.info.drm_major == 2 &&
rscreen->b.info.drm_minor >= 43;
+
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index eddb37d..7765c00 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -197,6 +197,19 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags,
rctx->rings.dma.flushing = false;
}
+static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
+{
+ struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+ unsigned latest = rctx->ws->query_value(rctx->ws,
+ RADEON_GPU_RESET_COUNTER);
+
+ if (rctx->gpu_reset_counter == latest)
+ return PIPE_NO_RESET;
+
+ rctx->gpu_reset_counter = latest;
+ return PIPE_UNKNOWN_CONTEXT_RESET;
+}
+
bool r600_common_context_init(struct r600_common_context *rctx,
struct r600_common_screen *rscreen)
{
@@ -223,6 +236,13 @@ bool r600_common_context_init(struct r600_common_context
*rctx,
rctx->b.memory_barrier = r600_memory_barrier;
rctx->b.flush = r600_flush_from_st;
+ if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
+ rctx->b.get_device_reset_status = r600_get_reset_status;
+ rctx->gpu_reset_counter =
+ rctx->ws->query_value(rctx->ws,
+ RADEON_GPU_RESET_COUNTER);
+ }
+
LIST_INITHEAD(&rctx->texture_buffers);
r600_init_context_texture_functions(rctx);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index faa6e0d..009cd72 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -356,6 +356,7 @@ struct r600_common_context {
enum chip_class chip_class;
struct r600_rings rings;
unsigned initial_gfx_cs_size;
+ unsigned gpu_reset_counter;
struct u_upload_mgr *uploader;
struct u_suballocator *allocator_so_filled_size;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index e68c30e..ac382e7 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -256,6 +256,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
+ case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
+ return sscreen->b.info.drm_major == 2 &&
sscreen->b.info.drm_minor >= 43;
+
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return sscreen->b.chip_class < CIK ||
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index a6f847f..5222ff9 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -56,6 +56,10 @@
#define RADEON_INFO_READ_REG 0x24
#endif
+#ifndef RADEON_INFO_GPU_RESET_COUNTER
+#define RADEON_INFO_GPU_RESET_COUNTER 0x25
+#endif
+
static struct util_hash_table *fd_tab = NULL;
pipe_static_mutex(fd_tab_mutex);
@@ -578,6 +582,10 @@ static uint64_t radeon_query_value(struct radeon_winsys
*rws,
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
"current-gpu-mclk", (uint32_t*)&retval);
return retval;
+ case RADEON_GPU_RESET_COUNTER:
+ radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
+ "gpu-reset-counter", (uint32_t*)&retval);
+ return retval;
}
return 0;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index ee0a904..aadc7d7 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -170,9 +170,10 @@ enum radeon_value_id {
RADEON_NUM_BYTES_MOVED,
RADEON_VRAM_USAGE,
RADEON_GTT_USAGE,
- RADEON_GPU_TEMPERATURE,
+ RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
RADEON_CURRENT_SCLK,
- RADEON_CURRENT_MCLK
+ RADEON_CURRENT_MCLK,
+ RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
};
enum radeon_bo_priority {
--
2.1.0
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