On Mon, May 04, 2015 at 02:18:37PM +0300, Francisco Jerez wrote:
> "Pohjolainen, Topi" <topi.pohjolai...@intel.com> writes:
>
> > On Sat, Apr 25, 2015 at 01:45:36AM +0300, Francisco Jerez wrote:
> >> "Pohjolainen, Topi" <topi.pohjolai...@intel.com> writes:
> >>
> >> > On Fri, Feb 27, 2015 at 05:34:55PM +0200, Francisco Jerez wrote:
> >> >> ---
> >> >> src/mesa/drivers/dri/i965/brw_defines.h | 4 +
> >> >> src/mesa/drivers/dri/i965/brw_eu.h | 24 +++
> >> >> src/mesa/drivers/dri/i965/brw_eu_emit.c | 169
> >> >> +++++++++++++++++++++
> >> >> src/mesa/drivers/dri/i965/brw_fs.cpp | 12 ++
> >> >> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 17 +++
> >> >> .../drivers/dri/i965/brw_schedule_instructions.cpp | 3 +
> >> >> src/mesa/drivers/dri/i965/brw_shader.cpp | 8 +
> >> >> src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 +
> >> >> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 18 +++
> >> >> 9 files changed, 261 insertions(+)
> >> >>
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> >> >> b/src/mesa/drivers/dri/i965/brw_defines.h
> >> >> index e56f49c..cf07da9 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> >> >> @@ -906,6 +906,10 @@ enum opcode {
> >> >> SHADER_OPCODE_UNTYPED_SURFACE_READ,
> >> >> SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
> >> >>
> >> >> + SHADER_OPCODE_TYPED_ATOMIC,
> >> >> + SHADER_OPCODE_TYPED_SURFACE_READ,
> >> >> + SHADER_OPCODE_TYPED_SURFACE_WRITE,
> >> >> +
> >> >> SHADER_OPCODE_GEN4_SCRATCH_READ,
> >> >> SHADER_OPCODE_GEN4_SCRATCH_WRITE,
> >> >> SHADER_OPCODE_GEN7_SCRATCH_READ,
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
> >> >> b/src/mesa/drivers/dri/i965/brw_eu.h
> >> >> index cad956b..ce9554b 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_eu.h
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_eu.h
> >> >> @@ -421,6 +421,30 @@ brw_untyped_surface_write(struct brw_compile *p,
> >> >> unsigned num_channels);
> >> >>
> >> >> void
> >> >> +brw_typed_atomic(struct brw_compile *p,
> >> >> + struct brw_reg dst,
> >> >> + struct brw_reg payload,
> >> >> + struct brw_reg surface,
> >> >> + unsigned atomic_op,
> >> >> + unsigned msg_length,
> >> >> + bool response_expected);
> >> >> +
> >> >> +void
> >> >> +brw_typed_surface_read(struct brw_compile *p,
> >> >> + struct brw_reg dst,
> >> >> + struct brw_reg payload,
> >> >> + struct brw_reg surface,
> >> >> + unsigned msg_length,
> >> >> + unsigned num_channels);
> >> >> +
> >> >> +void
> >> >> +brw_typed_surface_write(struct brw_compile *p,
> >> >> + struct brw_reg payload,
> >> >> + struct brw_reg surface,
> >> >> + unsigned msg_length,
> >> >> + unsigned num_channels);
> >> >> +
> >> >> +void
> >> >> brw_pixel_interpolator_query(struct brw_compile *p,
> >> >> struct brw_reg dest,
> >> >> struct brw_reg mrf,
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> >> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> >> index f5b8fa9..74f1fc1 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> >> @@ -2944,6 +2944,175 @@ brw_untyped_surface_write(struct brw_compile *p,
> >> >> p, insn, num_channels);
> >> >> }
> >> >>
> >> >> +static void
> >> >> +brw_set_dp_typed_atomic_message(struct brw_compile *p,
> >> >> + struct brw_inst *insn,
> >> >> + unsigned atomic_op,
> >> >> + bool response_expected)
> >> >> +{
> >> >> + const struct brw_context *brw = p->brw;
> >> >> + unsigned msg_control =
> >> >> + atomic_op | /* Atomic Operation Type: BRW_AOP_* */
> >> >> + (response_expected ? 1 << 5 : 0); /* Return data expected */
> >> >> +
> >> >> + if (brw->gen >= 8 || brw->is_haswell) {
> >> >> + if (brw_inst_access_mode(brw, p->current) == BRW_ALIGN_1) {
> >> >> + if (brw_inst_qtr_control(brw, p->current) ==
> >> >> GEN6_COMPRESSION_2Q)
> >> >> + msg_control |= 1 << 4; /* Use high 8 slots of the sample
> >> >> mask */
> >> >> +
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> +
> >> >> HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP);
> >> >> + } else {
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> +
> >> >> HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2);
> >> >> + }
> >> >> +
> >> >> + } else {
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> + GEN7_DATAPORT_RC_TYPED_ATOMIC_OP);
> >> >> +
> >> >> + if (brw_inst_qtr_control(brw, p->current) == GEN6_COMPRESSION_2Q)
> >> >> + msg_control |= 1 << 4; /* Use high 8 slots of the sample mask
> >> >> */
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_control(brw, insn, msg_control);
> >> >> +}
> >> >> +
> >> >> +void
> >> >> +brw_typed_atomic(struct brw_compile *p,
> >> >> + struct brw_reg dst,
> >> >> + struct brw_reg payload,
> >> >> + struct brw_reg surface,
> >> >> + unsigned atomic_op,
> >> >> + unsigned msg_length,
> >> >> + bool response_expected) {
> >> >> + const struct brw_context *brw = p->brw;
> >> >> + const unsigned sfid = (brw->gen >= 8 || brw->is_haswell ?
> >> >> + HSW_SFID_DATAPORT_DATA_CACHE_1 :
> >> >> + GEN6_SFID_DATAPORT_RENDER_CACHE);
> >> >> + const bool align1 = (brw_inst_access_mode(brw, p->current) ==
> >> >> BRW_ALIGN_1);
> >> >> + /* Mask out unused components -- See comment in
> >> >> brw_untyped_atomic(). */
> >> >> + const unsigned mask = (align1 ? WRITEMASK_XYZW : WRITEMASK_X);
> >> >> + struct brw_inst *insn = brw_send_indirect_surface_message(
> >> >> + p, sfid, brw_writemask(dst, mask), payload, surface, msg_length,
> >> >> + brw_surface_payload_size(p, response_expected,
> >> >> + brw->gen >= 8 || brw->is_haswell,
> >> >> false),
> >> >> + true);
> >
> > Did you mean to use the otherwise unneeded "align1" here instead of the
> > hardcoded "true"? This should match the behaviour of brw_untyped_atomic() in
> > this regard, right?
> >
> Nope, this is an actual asymmetry between untyped and typed surface
> messages, the former require a header in the fragment shader only, while
> the latter *always* require a header, that's the reason it's hardcoded
> to true here.
Right, you can drop the 'align1' variable then, it is unused.
>
> >> >> +
> >> >> + brw_set_dp_typed_atomic_message(
> >> >> + p, insn, atomic_op, response_expected);
> >> >> +}
> >> >> +
> >> >> +static void
> >> >> +brw_set_dp_typed_surface_read_message(struct brw_compile *p,
> >> >> + struct brw_inst *insn,
> >> >> + unsigned num_channels)
> >> >> +{
> >> >> + const struct brw_context *brw = p->brw;
> >> >> + /* Set mask of unused channels. */
> >> >> + unsigned msg_control = (0xf & (0xf << num_channels));
Small nit, you could use const here (like you do for everything else).
> >> >> +
> >> >> + if (brw->gen >= 8 || brw->is_haswell) {
> >> >> + if (brw_inst_access_mode(brw, p->current) == BRW_ALIGN_1) {
> >> >> + if (brw_inst_qtr_control(brw, p->current) ==
> >> >> GEN6_COMPRESSION_2Q)
> >> >> + msg_control |= 2 << 4; /* Use high 8 slots of the sample
> >> >> mask */
> >> >> + else
> >> >> + msg_control |= 1 << 4; /* Use low 8 slots of the sample
> >> >> mask */
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> +
> >> >> HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ);
> >> >> + } else {
> >> >> + if (brw_inst_access_mode(brw, p->current) == BRW_ALIGN_1) {
> >> >> + if (brw_inst_qtr_control(brw, p->current) ==
> >> >> GEN6_COMPRESSION_2Q)
> >> >> + msg_control |= 1 << 5; /* Use high 8 slots of the sample
> >> >> mask */
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> + GEN7_DATAPORT_RC_TYPED_SURFACE_READ);
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_control(brw, insn, msg_control);
> >> >> +}
> >> >> +
> >> >> +void
> >> >> +brw_typed_surface_read(struct brw_compile *p,
> >> >> + struct brw_reg dst,
> >> >> + struct brw_reg payload,
> >> >> + struct brw_reg surface,
> >> >> + unsigned msg_length,
> >> >> + unsigned num_channels)
> >> >> +{
> >> >> + const struct brw_context *brw = p->brw;
> >> >> + const unsigned sfid = (brw->gen >= 8 || brw->is_haswell ?
> >> >> + HSW_SFID_DATAPORT_DATA_CACHE_1 :
> >> >> + GEN6_SFID_DATAPORT_RENDER_CACHE);
> >> >> + struct brw_inst *insn = brw_send_indirect_surface_message(
> >> >
> >> > This call doesn't exist yet in upstream but I understood from you that
> >> > everything else up to here in this series is upstreamed. Am I missing
> >> > something?
> >> >
> >>
> >> No, it's not upstream because it's defined in PATCH 5 you haven't sent
> >> your R-b for AFAIK. Other patches up to this point are reviewed indeed.
> >
> > Right. This looks pretty consistent with untyped. I checked the message
> > control bits against IVB PRM and bspec, and they seem to be fine as well.
> >
> >>
> >> >> + p, sfid, dst, payload, surface, msg_length,
> >> >> + brw_surface_payload_size(p, num_channels,
> >> >> + brw->gen >= 8 || brw->is_haswell,
> >> >> false),
> >> >> + true);
> >
> > Here the same question about considering align1 mode? In
> > brw_untyped_surface_read() we check the access mode and pass it to
> > brw_surface_payload_size().
> >
> brw_untyped_surface_read() passes it as the header_present argument of
> brw_send_indirect_surface_message().
>
> Thank you Topi.
>
> >> >> +
> >> >> + brw_set_dp_typed_surface_read_message(
> >> >> + p, insn, num_channels);
> >> >> +}
> >> >> +
> >> >> +static void
> >> >> +brw_set_dp_typed_surface_write_message(struct brw_compile *p,
> >> >> + struct brw_inst *insn,
> >> >> + unsigned num_channels)
> >> >> +{
> >> >> + const struct brw_context *brw = p->brw;
> >> >> + /* Set mask of unused channels. */
> >> >> + unsigned msg_control = (0xf & (0xf << num_channels));
Same here.
Anyway:
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> >> >> +
> >> >> + if (brw->gen >= 8 || brw->is_haswell) {
> >> >> + if (brw_inst_access_mode(brw, p->current) == BRW_ALIGN_1) {
> >> >> + if (brw_inst_qtr_control(brw, p->current) ==
> >> >> GEN6_COMPRESSION_2Q)
> >> >> + msg_control |= 2 << 4; /* Use high 8 slots of the sample
> >> >> mask */
> >> >> + else
> >> >> + msg_control |= 1 << 4; /* Use low 8 slots of the sample
> >> >> mask */
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> +
> >> >> HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE);
> >> >> +
> >> >> + } else {
> >> >> + if (brw_inst_access_mode(brw, p->current) == BRW_ALIGN_1) {
> >> >> + if (brw_inst_qtr_control(brw, p->current) ==
> >> >> GEN6_COMPRESSION_2Q)
> >> >> + msg_control |= 1 << 5; /* Use high 8 slots of the sample
> >> >> mask */
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_type(brw, insn,
> >> >> + GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE);
> >> >> + }
> >> >> +
> >> >> + brw_inst_set_dp_msg_control(brw, insn, msg_control);
> >> >> +}
> >> >> +
> >> >> +void
> >> >> +brw_typed_surface_write(struct brw_compile *p,
> >> >> + struct brw_reg payload,
> >> >> + struct brw_reg surface,
> >> >> + unsigned msg_length,
> >> >> + unsigned num_channels)
> >> >> +{
> >> >> + const struct brw_context *brw = p->brw;
> >> >> + const unsigned sfid = (brw->gen >= 8 || brw->is_haswell ?
> >> >> + HSW_SFID_DATAPORT_DATA_CACHE_1 :
> >> >> + GEN6_SFID_DATAPORT_RENDER_CACHE);
> >> >> + const bool align1 = (brw_inst_access_mode(brw, p->current) ==
> >> >> BRW_ALIGN_1);
> >> >> + /* Mask out unused components -- See comment in
> >> >> brw_untyped_atomic(). */
> >> >> + const unsigned mask = (brw->gen == 7 && !brw->is_haswell && !align1
> >> >> ?
> >> >> + WRITEMASK_X : WRITEMASK_XYZW);
> >> >> + struct brw_inst *insn = brw_send_indirect_surface_message(
> >> >> + p, sfid, brw_writemask(brw_null_reg(), mask),
> >> >> + payload, surface, msg_length, 0, true);
> >> >> +
> >> >> + brw_set_dp_typed_surface_write_message(
> >> >> + p, insn, num_channels);
> >> >> +}
> >> >> +
> >> >> void
> >> >> brw_pixel_interpolator_query(struct brw_compile *p,
> >> >> struct brw_reg dest,
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> >> >> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> >> >> index 6d363f1..191d787 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> >> >> @@ -509,6 +509,9 @@ fs_inst::is_send_from_grf() const
> >> >> case SHADER_OPCODE_UNTYPED_ATOMIC:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> case SHADER_OPCODE_URB_WRITE_SIMD8:
> >> >> return true;
> >> >> case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
> >> >> @@ -933,6 +936,12 @@ fs_inst::regs_read(int arg) const
> >> >> return mlen;
> >> >> } else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE && arg ==
> >> >> 0) {
> >> >> return mlen;
> >> >> + } else if (opcode == SHADER_OPCODE_TYPED_ATOMIC && arg == 0) {
> >> >> + return mlen;
> >> >> + } else if (opcode == SHADER_OPCODE_TYPED_SURFACE_READ && arg == 0) {
> >> >> + return mlen;
> >> >> + } else if (opcode == SHADER_OPCODE_TYPED_SURFACE_WRITE && arg == 0)
> >> >> {
> >> >> + return mlen;
> >> >> } else if (opcode == FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET &&
> >> >> arg == 0) {
> >> >> return mlen;
> >> >> }
> >> >> @@ -1024,6 +1033,9 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
> >> >> case SHADER_OPCODE_UNTYPED_ATOMIC:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> case SHADER_OPCODE_URB_WRITE_SIMD8:
> >> >> case FS_OPCODE_INTERPOLATE_AT_CENTROID:
> >> >> case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> >> >> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> >> >> index 6e093cf..e80866b 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> >> >> @@ -1905,6 +1905,23 @@ fs_generator::generate_code(const cfg_t *cfg,
> >> >> int dispatch_width)
> >> >> inst->mlen, src[2].dw1.ud);
> >> >> break;
> >> >>
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
> >> >> + brw_typed_atomic(p, dst, src[0], src[1],
> >> >> + src[2].dw1.ud, inst->mlen,
> >> >> !inst->dst.is_null());
> >> >> + break;
> >> >> +
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
> >> >> + brw_typed_surface_read(p, dst, src[0], src[1],
> >> >> + inst->mlen, src[2].dw1.ud);
> >> >> + break;
> >> >> +
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
> >> >> + brw_typed_surface_write(p, src[0], src[1], inst->mlen,
> >> >> src[2].dw1.ud);
> >> >> + break;
> >> >> +
> >> >> case SHADER_OPCODE_FIND_LIVE_CHANNEL:
> >> >> brw_find_live_channel(p, dst);
> >> >> break;
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> >> >> b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> >> >> index 46b635c..808d839 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> >> >> @@ -340,6 +340,7 @@ schedule_node::set_latency_gen7(bool is_haswell)
> >> >> break;
> >> >>
> >> >> case SHADER_OPCODE_UNTYPED_ATOMIC:
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> /* Test code:
> >> >> * mov(8) g112<1>ud 0x00000000ud { align1
> >> >> WE_all 1Q };
> >> >> * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1
> >> >> WE_all };
> >> >> @@ -359,6 +360,8 @@ schedule_node::set_latency_gen7(bool is_haswell)
> >> >>
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> /* Test code:
> >> >> * mov(8) g112<1>UD 0x00000000UD { align1
> >> >> WE_all 1Q };
> >> >> * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1
> >> >> WE_all };
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> >> >> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> >> >> index b58796d..647355d 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> >> >> @@ -460,6 +460,12 @@ brw_instruction_name(enum opcode op)
> >> >> return "untyped_surface_read";
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> return "untyped_surface_write";
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + return "typed_atomic";
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + return "typed_surface_read";
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> + return "typed_surface_write";
> >> >>
> >> >> case SHADER_OPCODE_LOAD_PAYLOAD:
> >> >> return "load_payload";
> >> >> @@ -969,6 +975,8 @@ backend_instruction::has_side_effects() const
> >> >> switch (opcode) {
> >> >> case SHADER_OPCODE_UNTYPED_ATOMIC:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> case SHADER_OPCODE_URB_WRITE_SIMD8:
> >> >> case FS_OPCODE_FB_WRITE:
> >> >> return true;
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> >> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> >> index 736437f..174257b 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> >> @@ -259,6 +259,9 @@ vec4_instruction::is_send_from_grf()
> >> >> case SHADER_OPCODE_UNTYPED_ATOMIC:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> return true;
> >> >> default:
> >> >> return false;
> >> >> @@ -276,6 +279,9 @@ vec4_instruction::regs_read(unsigned arg) const
> >> >> case SHADER_OPCODE_UNTYPED_ATOMIC:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> >> >> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> return arg == 0 ? mlen : 1;
> >> >>
> >> >> case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> >> >> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> >> >> index 4c75b95..943c92a 100644
> >> >> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> >> >> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> >> >> @@ -1480,6 +1480,24 @@ vec4_generator::generate_code(const cfg_t *cfg)
> >> >> src[2].dw1.ud);
> >> >> break;
> >> >>
> >> >> + case SHADER_OPCODE_TYPED_ATOMIC:
> >> >> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
> >> >> + brw_typed_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
> >> >> inst->mlen,
> >> >> + !inst->dst.is_null());
> >> >> + break;
> >> >> +
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_READ:
> >> >> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
> >> >> + brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
> >> >> + src[2].dw1.ud);
> >> >> + break;
> >> >> +
> >> >> + case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> >> >> + assert(src[2].file == BRW_IMMEDIATE_VALUE);
> >> >> + brw_typed_surface_write(p, src[0], src[1], inst->mlen,
> >> >> + src[2].dw1.ud);
> >> >> + break;
> >> >> +
> >> >> case SHADER_OPCODE_FIND_LIVE_CHANNEL:
> >> >> brw_find_live_channel(p, dst);
> >> >> break;
> >> >> --
> >> >> 2.1.3
> >> >>
> >> >> _______________________________________________
> >> >> mesa-dev mailing list
> >> >> mesa-dev@lists.freedesktop.org
> >> >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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