From: Iago Toral Quiroga <ito...@igalia.com>
In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we need
to implement nir_intrinsic_load_uniform. Otherwise we would need a mapping to
match the output of nir_lower_io to the actual uniform registers we need to
use.
---
src/mesa/drivers/dri/i965/brw_nir.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 8700cb7..d81d823 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -101,10 +101,16 @@ brw_create_nir(struct brw_context *brw,
/* Get rid of split copies */
nir_optimize(nir);
- nir_assign_var_locations_direct_first(nir, &nir->uniforms,
- &nir->num_direct_uniforms,
- &nir->num_uniforms,
- is_scalar);
+ if (is_scalar) {
+ nir_assign_var_locations_direct_first(nir, &nir->uniforms,
+ &nir->num_direct_uniforms,
+ &nir->num_uniforms,
+ is_scalar);
+ } else {
+ nir_assign_var_locations(&nir->uniforms,
+ &nir->num_uniforms,
+ is_scalar);
+ }
nir_assign_var_locations(&nir->inputs, &nir->num_inputs, is_scalar);
nir_assign_var_locations(&nir->outputs, &nir->num_outputs, is_scalar);
--
2.1.4
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