On 24.07.2015 13:01, Dave Airlie wrote: > From: Dave Airlie <airl...@redhat.com> > > This adds support for fine derivatives and enables > ARB_derivative_control on radeonsi. > > (just fell out of my working out interpolation) > > v2: cleanup some bits, and try and write an > explaination.
Spelling: "explanation" > @@ -280,7 +281,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum > pipe_cap param) > return HAVE_LLVM >= 0x0305; > case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: > return HAVE_LLVM >= 0x0305 ? 4 : 0; > - > /* Unsupported features. */ > case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: > case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: > @@ -289,7 +289,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum > pipe_cap param) > case PIPE_CAP_USER_VERTEX_BUFFERS: > case PIPE_CAP_FAKE_SW_MSAA: > case PIPE_CAP_TEXTURE_GATHER_OFFSETS: > - case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: > + > case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: > case PIPE_CAP_SAMPLER_VIEW_TARGET: > case PIPE_CAP_VERTEXID_NOBASE: Looks like you removed the wrong blank line here. :) > diff --git a/src/gallium/drivers/radeonsi/si_shader.c > b/src/gallium/drivers/radeonsi/si_shader.c > index 5a3de96..9c3150d 100644 > --- a/src/gallium/drivers/radeonsi/si_shader.c > +++ b/src/gallium/drivers/radeonsi/si_shader.c > @@ -2799,6 +2799,24 @@ static void build_txq_intrinsic(const struct > lp_build_tgsi_action * action, > } > } > > +/* > + * SI implements derivatives using the local data store (LDS) > + * All writes to the LDS happen in all executing threads at > + * the same time. So all threads get a thread ID, and store > + * the src value they want to derive into the LDS. > + * Depending on whether it is doing coarse or fine derivatives > + * then masks the address to a top-left, top or left value > + * and reads back the value at that position. > + * It then reads back the value at the position either > + * 1 for DDX or 2 for DDY values later, and > + * calculates the difference. This value is the > + * derivative in that direction. > + */ It's not "a" thread ID but the thread ID (TID), which is a number 0..63 representing the thread's position in the wavefront. For the pixel shader, threads are grouped into quads of four pixels. The TIDs of the pixels of quad n are as follows: +------+------+ |4n + 0|4n + 1| +------+------+ |4n + 2|4n + 3| +------+------+ So, masking the TID with 0xfffffffc yields the TID of the top left pixel of the quad, masking with 0xfffffffd yields the TID of the top pixel of the current pixel's column, and masking with 0xfffffffe yields the TID of the left pixel of the current pixel's row. Adding 1 yields the TID of the pixel to the right of the left pixel, and adding 2 yields the TID of the pixel below the top pixel. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
