It's not guaranteed to have the same width as the instruction
generating the spilled variable.
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index f25f2ec..6a7ed64 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -738,7 +738,7 @@ fs_visitor::emit_spill(bblock_t *block, fs_inst *inst,
fs_reg src,
for (int i = 0; i < count / reg_size; i++) {
fs_inst *spill_inst =
- ibld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, bld.null_reg_f(), src);
+ ibld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, ibld.null_reg_f(), src);
src.reg_offset += reg_size;
spill_inst->offset = spill_offset + i * reg_size * REG_SIZE;
spill_inst->mlen = 1 + reg_size; /* header, value */
--
2.4.6
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