Since we really do not know what may occur in the future, pick a more
conservative value for thread counts until we know better what values are
correct. As far as I can tell, the old values will work fine, but some of the
registers seem to indicate that going even lower is possible and the purpose of
having early support is to enable as many configurations that can possibly
exist (we can trim things down after platforms begin shipping later).
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
src/mesa/drivers/dri/i965/brw_device_info.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
index f313b2b..75d1ecb 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -340,8 +340,10 @@ static const struct brw_device_info brw_device_info_bxt = {
.is_broxton = 1,
.gt = 1,
.has_llc = false,
- .max_vs_threads = 112,
- .max_gs_threads = 112,
+
+ /* XXX: These are preliminary thread counts and URB sizes. */
+ .max_vs_threads = 56,
+ .max_gs_threads = 56,
.max_wm_threads = 32,
.urb = {
.size = 64,
--
2.5.0
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