In preparation for a local batch manager with a new buffer object, first reduce the churn by renaming the existing buffer objects: s/drm_intel_bo/brw_bo/
We only have to be careful to leave the global screen drm_intel_bo as they are. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_batch.h | 42 +++++++++++++ src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 61 +++++++++---------- src/mesa/drivers/dri/i965/brw_draw.c | 2 +- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 +- src/mesa/drivers/dri/i965/brw_object_purgeable.c | 4 +- .../drivers/dri/i965/brw_performance_monitor.c | 6 +- src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +- src/mesa/drivers/dri/i965/brw_program.c | 4 +- src/mesa/drivers/dri/i965/brw_queryobj.c | 4 +- src/mesa/drivers/dri/i965/brw_sf_state.c | 2 +- src/mesa/drivers/dri/i965/brw_state_cache.c | 2 +- src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 24 ++++---- src/mesa/drivers/dri/i965/gen6_queryobj.c | 8 +-- src/mesa/drivers/dri/i965/gen7_sol_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_sol_state.c | 3 +- src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 10 ++-- src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4 +- src/mesa/drivers/dri/i965/intel_blit.c | 68 +++++++++++----------- src/mesa/drivers/dri/i965/intel_blit.h | 34 +++++------ src/mesa/drivers/dri/i965/intel_buffer_objects.c | 14 ++--- src/mesa/drivers/dri/i965/intel_buffer_objects.h | 16 ++--- src/mesa/drivers/dri/i965/intel_fbo.c | 4 +- src/mesa/drivers/dri/i965/intel_fbo.h | 4 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 12 ++-- src/mesa/drivers/dri/i965/intel_pixel_draw.c | 2 +- src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.h | 6 +- src/mesa/drivers/dri/i965/intel_syncobj.c | 2 +- src/mesa/drivers/dri/i965/intel_tex.c | 6 +- src/mesa/drivers/dri/i965/intel_tex_image.c | 4 +- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +- src/mesa/drivers/dri/i965/intel_upload.c | 4 +- 38 files changed, 213 insertions(+), 168 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/brw_batch.h diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index dfdad75..a007440 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -1,4 +1,5 @@ i965_FILES = \ + brw_batch.h \ brw_binding_tables.c \ brw_blorp_blit.cpp \ brw_blorp_blit_eu.cpp \ diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h new file mode 100644 index 0000000..7268e26 --- /dev/null +++ b/src/mesa/drivers/dri/i965/brw_batch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Chris Wilson <ch...@chris-wilson.co.uk> + */ + +#ifndef BRW_BATCH_H +#define BRW_BATCH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <intel_bufmgr.h> + +typedef drm_intel_bo brw_bo; + +#ifdef __cplusplus +} +#endif + +#endif /* BRW_BATCH_H */ diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 8e02c69..8b2d006 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1350,7 +1350,7 @@ intel_process_dri2_buffer(struct brw_context *brw, const char *buffer_name) { struct gl_framebuffer *fb = drawable->driverPrivate; - drm_intel_bo *bo; + brw_bo *bo; if (!rb) return; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 73fc7b8..7fc65e5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -39,6 +39,7 @@ #include "main/macros.h" #include "main/mm.h" #include "main/mtypes.h" +#include "brw_batch.h" #include "brw_structs.h" #include "intel_aub.h" #include "program/prog_parameter.h" @@ -791,7 +792,7 @@ struct brw_cache { struct brw_context *brw; struct brw_cache_item **items; - drm_intel_bo *bo; + brw_bo *bo; GLuint size, n_items; uint32_t next_offset; @@ -830,7 +831,7 @@ enum shader_time_shader_type { struct brw_vertex_buffer { /** Buffer object containing the uploaded vertex data */ - drm_intel_bo *bo; + brw_bo *bo; uint32_t offset; /** Byte stride between elements in the uploaded array */ GLuint stride; @@ -849,7 +850,7 @@ struct brw_query_object { struct gl_query_object Base; /** Last query BO associated with this query. */ - drm_intel_bo *bo; + brw_bo *bo; /** Last index in bo with query data for this object. */ int last_index; @@ -866,9 +867,9 @@ enum brw_gpu_ring { struct intel_batchbuffer { /** Current batchbuffer being queued up. */ - drm_intel_bo *bo; + brw_bo *bo; /** Last BO submitted to the hardware. Used for glFinish(). */ - drm_intel_bo *last_bo; + brw_bo *last_bo; #ifdef DEBUG uint16_t emit, total; @@ -895,7 +896,7 @@ struct brw_transform_feedback_object { struct gl_transform_feedback_object base; /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */ - drm_intel_bo *offset_bo; + brw_bo *offset_bo; /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */ bool zero_offsets; @@ -908,7 +909,7 @@ struct brw_transform_feedback_object { * @{ */ uint64_t prims_generated[BRW_MAX_XFB_STREAMS]; - drm_intel_bo *prim_count_bo; + brw_bo *prim_count_bo; unsigned prim_count_buffer_index; /**< in number of uint64_t units */ /** @} */ @@ -934,7 +935,7 @@ struct brw_stage_state * Optional scratch buffer used to store spilled register values and * variably-indexed GRF arrays. */ - drm_intel_bo *scratch_bo; + brw_bo *scratch_bo; /** Offset in the program cache to the program */ uint32_t prog_offset; @@ -1002,7 +1003,7 @@ struct brw_context bool rw, bool for_gather); void (*emit_buffer_surface_state)(struct brw_context *brw, uint32_t *out_offset, - drm_intel_bo *bo, + brw_bo *bo, unsigned buffer_offset, unsigned surface_format, unsigned buffer_size, @@ -1035,11 +1036,11 @@ struct brw_context drm_intel_context *hw_ctx; /** BO for post-sync nonzero writes for gen6 workaround. */ - drm_intel_bo *workaround_bo; + brw_bo *workaround_bo; uint8_t pipe_controls_since_last_cs_stall; /** - * Set of drm_intel_bo * that have been rendered to within this batchbuffer + * Set of brw_bo* that have been rendered to within this batchbuffer * and would need flushing before being used from another cache domain that * isn't coherent with it (i.e. the sampler). */ @@ -1057,7 +1058,7 @@ struct brw_context bool no_batch_wrap; struct { - drm_intel_bo *bo; + brw_bo *bo; uint32_t next_offset; } upload; @@ -1070,7 +1071,7 @@ struct brw_context bool front_buffer_dirty; /** Framerate throttling: @{ */ - drm_intel_bo *throttle_batch[2]; + brw_bo *throttle_batch[2]; /* Limit the number of outstanding SwapBuffers by waiting for an earlier * frame of rendering to complete. This gives a very precise cap to the @@ -1179,7 +1180,7 @@ struct brw_context * Buffer and offset used for GL_ARB_shader_draw_parameters * (for now, only gl_BaseVertex). */ - drm_intel_bo *draw_params_bo; + brw_bo *draw_params_bo; uint32_t draw_params_offset; } draw; @@ -1219,7 +1220,7 @@ struct brw_context const struct _mesa_index_buffer *ib; /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */ - drm_intel_bo *bo; + brw_bo *bo; GLuint type; /* Offset to index buffer index to use in CMD_3D_PRIM so that we can @@ -1304,7 +1305,7 @@ struct brw_context * Pointer to the (intel_upload.c-generated) BO containing the uniforms * for upload to the CURBE. */ - drm_intel_bo *curbe_bo; + brw_bo *curbe_bo; /** Offset within curbe_bo of space for current curbe entry */ GLuint curbe_offset; } curbe; @@ -1394,7 +1395,7 @@ struct brw_context * Buffer object used in place of multisampled null render targets on * Gen6. See brw_emit_null_surface_state(). */ - drm_intel_bo *multisampled_null_render_target_bo; + brw_bo *multisampled_null_render_target_bo; uint32_t fast_clear_op; } wm; @@ -1405,7 +1406,7 @@ struct brw_context /* RS hardware binding table */ struct { - drm_intel_bo *bo; + brw_bo *bo; uint32_t next_offset; } hw_bt_pool; @@ -1437,7 +1438,7 @@ struct brw_context * A buffer object storing OA counter snapshots taken at the start and * end of each batch (creating "bookends" around the batch). */ - drm_intel_bo *bookend_bo; + brw_bo *bookend_bo; /** The number of snapshots written to bookend_bo. */ int bookend_snapshots; @@ -1508,7 +1509,7 @@ struct brw_context int basevertex; struct { - drm_intel_bo *bo; + brw_bo *bo; const char **names; int *ids; enum shader_time_shader_type *types; @@ -1621,10 +1622,10 @@ void brw_emit_query_end(struct brw_context *brw); /** gen6_queryobj.c */ void gen6_init_queryobj_functions(struct dd_function_table *functions); -void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx); -void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx); +void brw_write_timestamp(struct brw_context *brw, brw_bo *bo, int idx); +void brw_write_depth_count(struct brw_context *brw, brw_bo *bo, int idx); void brw_store_register_mem64(struct brw_context *brw, - drm_intel_bo *bo, uint32_t reg, int idx); + brw_bo *bo, uint32_t reg, int idx); /** brw_conditional_render.c */ void brw_init_conditional_render_functions(struct dd_function_table *functions); @@ -1633,12 +1634,12 @@ bool brw_check_conditional_render(struct brw_context *brw); /** intel_batchbuffer.c */ void brw_load_register_mem(struct brw_context *brw, uint32_t reg, - drm_intel_bo *bo, + brw_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset); void brw_load_register_mem64(struct brw_context *brw, uint32_t reg, - drm_intel_bo *bo, + brw_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset); @@ -1661,7 +1662,7 @@ void brwInitFragProgFuncs( struct dd_function_table *functions ); int brw_get_scratch_size(int size); void brw_get_scratch_bo(struct brw_context *brw, - drm_intel_bo **scratch_bo, int size); + brw_bo **scratch_bo, int size); void brw_init_shader_time(struct brw_context *brw); int brw_get_shader_time_index(struct brw_context *brw, struct gl_shader_program *shader_prog, @@ -1721,7 +1722,7 @@ void brw_prepare_vertices(struct brw_context *brw); /* brw_wm_surface_state.c */ void brw_init_surface_formats(struct brw_context *brw); void brw_create_constant_surface(struct brw_context *brw, - drm_intel_bo *bo, + brw_bo *bo, uint32_t offset, uint32_t size, uint32_t *out_offset, @@ -1756,9 +1757,9 @@ void brw_perf_monitor_new_batch(struct brw_context *brw); void brw_perf_monitor_finish_batch(struct brw_context *brw); /* intel_buffer_objects.c */ -int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable, +int brw_bo_map(struct brw_context *brw, brw_bo *bo, int write_enable, const char *bo_name); -int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo, +int brw_bo_map_gtt(struct brw_context *brw, brw_bo *bo, const char *bo_name); /* intel_extensions.c */ @@ -2022,7 +2023,7 @@ void brw_fini_pipe_control(struct brw_context *brw); void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, - drm_intel_bo *bo, uint32_t offset, + brw_bo *bo, uint32_t offset, uint32_t imm_lower, uint32_t imm_upper); void brw_emit_mi_flush(struct brw_context *brw); void brw_emit_post_sync_nonzero_flush(struct brw_context *brw); diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 611e585..6dc0fd8 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -220,7 +220,7 @@ brw_emit_prim(struct brw_context *brw, /* If indirect, emit a bunch of loads from the indirect BO. */ if (prim->is_indirect) { struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer; - drm_intel_bo *bo = intel_bufferobj_buffer(brw, + brw_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_object(indirect_buffer), prim->indirect_offset, 5 * sizeof(GLuint)); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 076f075..44e40f1 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -606,7 +606,7 @@ brw_prepare_shader_draw_parameters(struct brw_context *brw) static uint32_t * emit_vertex_buffer_state(struct brw_context *brw, unsigned buffer_nr, - drm_intel_bo *bo, + brw_bo *bo, unsigned bo_ending_address, unsigned bo_offset, unsigned stride, @@ -865,7 +865,7 @@ brw_upload_indices(struct brw_context *brw) struct gl_context *ctx = &brw->ctx; const struct _mesa_index_buffer *index_buffer = brw->ib.ib; GLuint ib_size; - drm_intel_bo *old_bo = brw->ib.bo; + brw_bo *old_bo = brw->ib.bo; struct gl_buffer_object *bufferobj; GLuint offset; GLuint ib_type_size; @@ -906,7 +906,7 @@ brw_upload_indices(struct brw_context *brw) ctx->Driver.UnmapBuffer(ctx, bufferobj, MAP_INTERNAL); } else { - drm_intel_bo *bo = + brw_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj), offset, ib_size); if (bo != brw->ib.bo) { diff --git a/src/mesa/drivers/dri/i965/brw_object_purgeable.c b/src/mesa/drivers/dri/i965/brw_object_purgeable.c index 20f66f2..8d7ebdb 100644 --- a/src/mesa/drivers/dri/i965/brw_object_purgeable.c +++ b/src/mesa/drivers/dri/i965/brw_object_purgeable.c @@ -38,7 +38,7 @@ #include "intel_mipmap_tree.h" static GLenum -intel_buffer_purgeable(drm_intel_bo *buffer) +intel_buffer_purgeable(brw_bo *buffer) { int retained = 0; @@ -101,7 +101,7 @@ intel_render_object_purgeable(struct gl_context * ctx, } static GLenum -intel_buffer_unpurgeable(drm_intel_bo *buffer) +intel_buffer_unpurgeable(brw_bo *buffer) { int retained; diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c index f5f180e..12e3285 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c +++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c @@ -70,7 +70,7 @@ struct brw_perf_monitor_object /** * BO containing OA counter snapshots at monitor Begin/End time. */ - drm_intel_bo *oa_bo; + brw_bo *oa_bo; /** Indexes into bookend_bo (snapshot numbers) for various segments. */ int oa_head_end; @@ -91,7 +91,7 @@ struct brw_perf_monitor_object * BO containing starting and ending snapshots for any active pipeline * statistics counters. */ - drm_intel_bo *pipeline_stats_bo; + brw_bo *pipeline_stats_bo; /** * Storage for final pipeline statistics counter results. @@ -702,7 +702,7 @@ stop_oa_counters(struct brw_context *brw) */ static void emit_mi_report_perf_count(struct brw_context *brw, - drm_intel_bo *bo, + brw_bo *bo, uint32_t offset_in_bytes, uint32_t report_id) { diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 366f987..36f74d6 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -134,7 +134,7 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) */ void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, - drm_intel_bo *bo, uint32_t offset, + brw_bo *bo, uint32_t offset, uint32_t imm_lower, uint32_t imm_upper) { if (brw->gen >= 8) { diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 2157b86..c52a393 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -261,9 +261,9 @@ brw_get_scratch_size(int size) void brw_get_scratch_bo(struct brw_context *brw, - drm_intel_bo **scratch_bo, int size) + brw_bo **scratch_bo, int size) { - drm_intel_bo *old_bo = *scratch_bo; + brw_bo *old_bo = *scratch_bo; if (old_bo && old_bo->size < size) { drm_intel_bo_unreference(old_bo); diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 3c0547f..cc68f17 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -47,7 +47,7 @@ * Emit PIPE_CONTROLs to write the current GPU timestamp into a buffer. */ void -brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) +brw_write_timestamp(struct brw_context *brw, brw_bo *query_bo, int idx) { if (brw->gen == 6) { /* Emit Sandybridge workaround flush: */ @@ -64,7 +64,7 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) * Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer. */ void -brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx) +brw_write_depth_count(struct brw_context *brw, brw_bo *query_bo, int idx) { uint32_t flags; diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index b126f82..bab155a 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -133,7 +133,7 @@ static void upload_sf_unit( struct brw_context *brw ) { struct gl_context *ctx = &brw->ctx; struct brw_sf_unit_state *sf; - drm_intel_bo *bo = brw->batch.bo; + brw_bo *bo = brw->batch.bo; int chipset_max_threads; bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index 546efc5..7c1a6e3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -168,7 +168,7 @@ static void brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size) { struct brw_context *brw = cache->brw; - drm_intel_bo *new_bo; + brw_bo *new_bo; new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64); if (brw->has_llc) diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index b2f91bd..b322db8 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -74,7 +74,7 @@ brw_upload_pull_constants(struct brw_context *brw, /* BRW_NEW_*_PROG_DATA | _NEW_PROGRAM_CONSTANTS */ uint32_t size = prog_data->nr_pull_params * 4; - drm_intel_bo *const_bo = NULL; + brw_bo *const_bo = NULL; uint32_t const_offset; gl_constant_value *constants = intel_upload_space(brw, size, 64, &const_bo, &const_offset); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 3250eb8..60f2aa6 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -242,7 +242,7 @@ brw_get_texture_swizzle(const struct gl_context *ctx, static void gen4_emit_buffer_surface_state(struct brw_context *brw, uint32_t *out_offset, - drm_intel_bo *bo, + brw_bo *bo, unsigned buffer_offset, unsigned surface_format, unsigned buffer_size, @@ -284,7 +284,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, struct intel_buffer_object *intel_obj = intel_buffer_object(tObj->BufferObject); uint32_t size = tObj->BufferSize; - drm_intel_bo *bo = NULL; + brw_bo *bo = NULL; mesa_format format = tObj->_BufferObjectFormat; uint32_t brw_format = brw_format_for_mesa_format(format); int texel_size = _mesa_get_format_bytes(format); @@ -395,10 +395,10 @@ brw_update_texture_surface(struct gl_context *ctx, */ void brw_create_constant_surface(struct brw_context *brw, - drm_intel_bo *bo, - uint32_t offset, - uint32_t size, - uint32_t *out_offset, + brw_bo *bo, + uint32_t offset, + uint32_t size, + uint32_t *out_offset, bool dword_pitch) { uint32_t stride = dword_pitch ? 4 : 16; @@ -423,9 +423,9 @@ brw_update_sol_surface(struct brw_context *brw, { struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj); uint32_t offset_bytes = 4 * offset_dwords; - drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, - offset_bytes, - buffer_obj->Size - offset_bytes); + brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo, + offset_bytes, + buffer_obj->Size - offset_bytes); uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, out_offset); uint32_t pitch_minus_1 = 4*stride_dwords - 1; @@ -559,7 +559,7 @@ brw_emit_null_surface_state(struct brw_context *brw, * - Surface Format must be R8G8B8A8_UNORM. */ unsigned surface_type = BRW_SURFACE_NULL; - drm_intel_bo *bo = NULL; + brw_bo *bo = NULL; unsigned pitch_minus_1 = 0; uint32_t multisampling_state = 0; uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, @@ -903,7 +903,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding]; intel_bo = intel_buffer_object(binding->BufferObject); - drm_intel_bo *bo = + brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo, binding->Offset, binding->BufferObject->Size - binding->Offset); @@ -962,7 +962,7 @@ brw_upload_abo_surfaces(struct brw_context *brw, &ctx->AtomicBufferBindings[prog->AtomicBuffers[i].Binding]; struct intel_buffer_object *intel_bo = intel_buffer_object(binding->BufferObject); - drm_intel_bo *bo = intel_bufferobj_buffer( + brw_bo *bo = intel_bufferobj_buffer( brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset); brw->vtbl.emit_buffer_surface_state(brw, &surf_offsets[i], bo, diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index f474c4b..b34268e 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -49,7 +49,7 @@ */ void brw_store_register_mem64(struct brw_context *brw, - drm_intel_bo *bo, uint32_t reg, int idx) + brw_bo *bo, uint32_t reg, int idx) { assert(brw->gen >= 6); @@ -83,7 +83,7 @@ brw_store_register_mem64(struct brw_context *brw, static void write_primitives_generated(struct brw_context *brw, - drm_intel_bo *query_bo, int stream, int idx) + brw_bo *query_bo, int stream, int idx) { brw_emit_mi_flush(brw); @@ -97,7 +97,7 @@ write_primitives_generated(struct brw_context *brw, static void write_xfb_primitives_written(struct brw_context *brw, - drm_intel_bo *bo, int stream, int idx) + brw_bo *bo, int stream, int idx) { brw_emit_mi_flush(brw); @@ -118,7 +118,7 @@ pipeline_target_to_index(int target) } static void -emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo, +emit_pipeline_stat(struct brw_context *brw, brw_bo *bo, int stream, int target, int idx) { /* One source of confusion is the tessellation shader statistics. The diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c index 67004b5..396d029 100644 --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c @@ -52,7 +52,7 @@ upload_3dstate_so_buffers(struct brw_context *brw) for (i = 0; i < 4; i++) { struct intel_buffer_object *bufferobj = intel_buffer_object(xfb_obj->Buffers[i]); - drm_intel_bo *bo; + brw_bo *bo; uint32_t start, end; uint32_t stride; diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 5a9241d..1885aed 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -220,7 +220,7 @@ gen7_check_surface_setup(uint32_t *surf, bool is_render_target) static void gen7_emit_buffer_surface_state(struct brw_context *brw, uint32_t *out_offset, - drm_intel_bo *bo, + brw_bo *bo, unsigned buffer_offset, unsigned surface_format, unsigned buffer_size, diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c b/src/mesa/drivers/dri/i965/gen8_sol_state.c index b2f9c2e..3c06df3 100644 --- a/src/mesa/drivers/dri/i965/gen8_sol_state.c +++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c @@ -69,8 +69,7 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw) uint32_t start = xfb_obj->Offset[i]; assert(start % 4 == 0); uint32_t end = ALIGN(start + xfb_obj->Size[i], 4); - drm_intel_bo *bo = - intel_bufferobj_buffer(brw, bufferobj, start, end - start); + brw_bo *bo = intel_bufferobj_buffer(brw, bufferobj, start, end - start); assert(end <= bo->size); perf_debug("Missing MOCS setup for 3DSTATE_SO_BUFFER."); diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 228bee7..e6cd503 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -144,7 +144,7 @@ allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index) static void gen8_emit_buffer_surface_state(struct brw_context *brw, uint32_t *out_offset, - drm_intel_bo *bo, + brw_bo *bo, unsigned buffer_offset, unsigned surface_format, unsigned buffer_size, diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 85f20a0..44512be 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -406,7 +406,7 @@ _intel_batchbuffer_flush(struct brw_context *brw, */ uint32_t intel_batchbuffer_reloc(struct brw_context *brw, - drm_intel_bo *buffer, uint32_t offset, + brw_bo *buffer, uint32_t offset, uint32_t read_domains, uint32_t write_domain, uint32_t delta) { @@ -427,7 +427,7 @@ intel_batchbuffer_reloc(struct brw_context *brw, uint64_t intel_batchbuffer_reloc64(struct brw_context *brw, - drm_intel_bo *buffer, uint32_t offset, + brw_bo *buffer, uint32_t offset, uint32_t read_domains, uint32_t write_domain, uint32_t delta) { @@ -458,7 +458,7 @@ intel_batchbuffer_data(struct brw_context *brw, static void load_sized_register_mem(struct brw_context *brw, uint32_t reg, - drm_intel_bo *bo, + brw_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset, int size) @@ -490,7 +490,7 @@ load_sized_register_mem(struct brw_context *brw, void brw_load_register_mem(struct brw_context *brw, uint32_t reg, - drm_intel_bo *bo, + brw_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset) { @@ -500,7 +500,7 @@ brw_load_register_mem(struct brw_context *brw, void brw_load_register_mem64(struct brw_context *brw, uint32_t reg, - drm_intel_bo *bo, + brw_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset) { diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index c258579..48d6f5a 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -59,13 +59,13 @@ void intel_batchbuffer_data(struct brw_context *brw, enum brw_gpu_ring ring); uint32_t intel_batchbuffer_reloc(struct brw_context *brw, - drm_intel_bo *buffer, + brw_bo *buffer, uint32_t offset, uint32_t read_domains, uint32_t write_domain, uint32_t delta); uint64_t intel_batchbuffer_reloc64(struct brw_context *brw, - drm_intel_bo *buffer, + brw_bo *buffer, uint32_t offset, uint32_t read_domains, uint32_t write_domain, diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 90cb0ea..91ffcef 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -397,11 +397,11 @@ alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling) static bool can_fast_copy_blit(struct brw_context *brw, - drm_intel_bo *src_buffer, + brw_bo *src_buffer, int16_t src_x, int16_t src_y, uintptr_t src_offset, uint32_t src_pitch, uint32_t src_tiling, uint32_t src_tr_mode, - drm_intel_bo *dst_buffer, + brw_bo *dst_buffer, int16_t dst_x, int16_t dst_y, uintptr_t dst_offset, uint32_t dst_pitch, uint32_t dst_tiling, uint32_t dst_tr_mode, @@ -505,26 +505,26 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode, */ bool intelEmitCopyBlit(struct brw_context *brw, - GLuint cpp, - GLshort src_pitch, - drm_intel_bo *src_buffer, - GLuint src_offset, - uint32_t src_tiling, - uint32_t src_tr_mode, - GLshort dst_pitch, - drm_intel_bo *dst_buffer, - GLuint dst_offset, - uint32_t dst_tiling, - uint32_t dst_tr_mode, - GLshort src_x, GLshort src_y, - GLshort dst_x, GLshort dst_y, - GLshort w, GLshort h, - GLenum logic_op) + GLuint cpp, + GLshort src_pitch, + brw_bo *src_buffer, + GLuint src_offset, + uint32_t src_tiling, + uint32_t src_tr_mode, + GLshort dst_pitch, + brw_bo *dst_buffer, + GLuint dst_offset, + uint32_t dst_tiling, + uint32_t dst_tr_mode, + GLshort src_x, GLshort src_y, + GLshort dst_x, GLshort dst_y, + GLshort w, GLshort h, + GLenum logic_op) { GLuint CMD, BR13, pass = 0; int dst_y2 = dst_y + h; int dst_x2 = dst_x + w; - drm_intel_bo *aper_array[3]; + brw_bo *aper_array[3]; bool dst_y_tiled = dst_tiling == I915_TILING_Y; bool src_y_tiled = src_tiling == I915_TILING_Y; bool use_fast_copy_blit = false; @@ -696,16 +696,16 @@ intelEmitCopyBlit(struct brw_context *brw, bool intelEmitImmediateColorExpandBlit(struct brw_context *brw, - GLuint cpp, - GLubyte *src_bits, GLuint src_size, - GLuint fg_color, - GLshort dst_pitch, - drm_intel_bo *dst_buffer, - GLuint dst_offset, - uint32_t dst_tiling, - GLshort x, GLshort y, - GLshort w, GLshort h, - GLenum logic_op) + GLuint cpp, + GLubyte *src_bits, GLuint src_size, + GLuint fg_color, + GLshort dst_pitch, + brw_bo *dst_buffer, + GLuint dst_offset, + uint32_t dst_tiling, + GLshort x, GLshort y, + GLshort w, GLshort h, + GLenum logic_op) { int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; @@ -784,11 +784,11 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, */ void intel_emit_linear_blit(struct brw_context *brw, - drm_intel_bo *dst_bo, - unsigned int dst_offset, - drm_intel_bo *src_bo, - unsigned int src_offset, - unsigned int size) + brw_bo *dst_bo, + unsigned int dst_offset, + brw_bo *src_bo, + unsigned int src_offset, + unsigned int size) { struct gl_context *ctx = &brw->ctx; GLuint pitch, height; @@ -853,7 +853,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, { uint32_t BR13, CMD; int pitch, cpp; - drm_intel_bo *aper_array[2]; + brw_bo *aper_array[2]; pitch = mt->pitch; cpp = mt->cpp; diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h index c3d19a5..3127b1e 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.h +++ b/src/mesa/drivers/dri/i965/intel_blit.h @@ -34,12 +34,12 @@ bool intelEmitCopyBlit(struct brw_context *brw, GLuint cpp, GLshort src_pitch, - drm_intel_bo *src_buffer, + brw_bo *src_buffer, GLuint src_offset, uint32_t src_tiling, uint32_t src_tr_mode, GLshort dst_pitch, - drm_intel_bo *dst_buffer, + brw_bo *dst_buffer, GLuint dst_offset, uint32_t dst_tiling, uint32_t dst_tr_mode, @@ -62,21 +62,21 @@ bool intel_miptree_blit(struct brw_context *brw, bool intelEmitImmediateColorExpandBlit(struct brw_context *brw, - GLuint cpp, - GLubyte *src_bits, GLuint src_size, - GLuint fg_color, - GLshort dst_pitch, - drm_intel_bo *dst_buffer, - GLuint dst_offset, - uint32_t dst_tiling, - GLshort x, GLshort y, - GLshort w, GLshort h, - GLenum logic_op); + GLuint cpp, + GLubyte *src_bits, GLuint src_size, + GLuint fg_color, + GLshort dst_pitch, + brw_bo *dst_buffer, + GLuint dst_offset, + uint32_t dst_tiling, + GLshort x, GLshort y, + GLshort w, GLshort h, + GLenum logic_op); void intel_emit_linear_blit(struct brw_context *brw, - drm_intel_bo *dst_bo, - unsigned int dst_offset, - drm_intel_bo *src_bo, - unsigned int src_offset, - unsigned int size); + brw_bo *dst_bo, + unsigned int dst_offset, + brw_bo *src_bo, + unsigned int src_offset, + unsigned int size); #endif diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index 77f634c..fec8743 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c @@ -48,7 +48,7 @@ */ int brw_bo_map(struct brw_context *brw, - drm_intel_bo *bo, int write_enable, + brw_bo *bo, int write_enable, const char *bo_name) { if (likely(!brw->perf_debug) || !drm_intel_bo_busy(bo)) @@ -65,7 +65,7 @@ brw_bo_map(struct brw_context *brw, } int -brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo, const char *bo_name) +brw_bo_map_gtt(struct brw_context *brw, brw_bo *bo, const char *bo_name) { if (likely(!brw->perf_debug) || !drm_intel_bo_busy(bo)) return drm_intel_gem_bo_map_gtt(bo); @@ -95,7 +95,7 @@ mark_buffer_inactive(struct intel_buffer_object *intel_obj) intel_obj->gpu_active_end = 0; } -/** Allocates a new drm_intel_bo to store the data for the buffer object. */ +/** Allocates a new brw_bo to store the data for the buffer object. */ static void alloc_buffer_object(struct brw_context *brw, struct intel_buffer_object *intel_obj) @@ -284,8 +284,8 @@ brw_buffer_subdata(struct gl_context *ctx, (long)offset, (long)offset + size, (long)(size/1024), intel_obj->gpu_active_start, intel_obj->gpu_active_end); - drm_intel_bo *temp_bo = - drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64); + brw_bo *temp_bo = + drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64); drm_intel_bo_subdata(temp_bo, 0, size, data); @@ -580,7 +580,7 @@ brw_unmap_buffer(struct gl_context *ctx, * Anywhere that uses buffer objects in the pipeline should be using this to * mark the range of the buffer that is being accessed by the pipeline. */ -drm_intel_bo * +brw_bo * intel_bufferobj_buffer(struct brw_context *brw, struct intel_buffer_object *intel_obj, uint32_t offset, uint32_t size) @@ -614,7 +614,7 @@ brw_copy_buffer_subdata(struct gl_context *ctx, struct brw_context *brw = brw_context(ctx); struct intel_buffer_object *intel_src = intel_buffer_object(src); struct intel_buffer_object *intel_dst = intel_buffer_object(dst); - drm_intel_bo *src_bo, *dst_bo; + brw_bo *src_bo, *dst_bo; if (size == 0) return; diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.h b/src/mesa/drivers/dri/i965/intel_buffer_objects.h index d46feac..a31ac0d 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.h +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.h @@ -41,9 +41,9 @@ struct gl_buffer_object; struct intel_buffer_object { struct gl_buffer_object Base; - drm_intel_bo *buffer; /* the low-level buffer manager's buffer handle */ + brw_bo *buffer; /* the low-level buffer manager's buffer handle */ - drm_intel_bo *range_map_bo[MAP_COUNT]; + brw_bo *range_map_bo[MAP_COUNT]; /** * Alignment offset from the range_map_bo temporary mapping to the returned @@ -85,22 +85,22 @@ struct intel_buffer_object /* Get the bm buffer associated with a GL bufferobject: */ -drm_intel_bo *intel_bufferobj_buffer(struct brw_context *brw, - struct intel_buffer_object *obj, - uint32_t offset, - uint32_t size); +brw_bo *intel_bufferobj_buffer(struct brw_context *brw, + struct intel_buffer_object *obj, + uint32_t offset, + uint32_t size); void intel_upload_data(struct brw_context *brw, const void *data, uint32_t size, uint32_t alignment, - drm_intel_bo **out_bo, + brw_bo **out_bo, uint32_t *out_offset); void *intel_upload_space(struct brw_context *brw, uint32_t size, uint32_t alignment, - drm_intel_bo **out_bo, + brw_bo **out_bo, uint32_t *out_offset); void intel_upload_finish(struct brw_context *brw); diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 47518d9..b22931e 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -1056,7 +1056,7 @@ brw_render_cache_set_clear(struct brw_context *brw) } void -brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo) +brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo) { _mesa_set_add(brw->render_cache, bo); } @@ -1074,7 +1074,7 @@ brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo) * different caches within a batchbuffer, it's all our responsibility. */ void -brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo) +brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo) { if (!_mesa_set_search(brw->render_cache, bo)) return; diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h index c7cc570..aad5bf7 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.h +++ b/src/mesa/drivers/dri/i965/intel_fbo.h @@ -241,8 +241,8 @@ intel_renderbuffer_upsample(struct brw_context *brw, struct intel_renderbuffer *irb); void brw_render_cache_set_clear(struct brw_context *brw); -void brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo); -void brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo); +void brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo); +void brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo); unsigned intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 45a244e..59660c0 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -727,7 +727,7 @@ intel_miptree_create(struct brw_context *brw, struct intel_mipmap_tree * intel_miptree_create_for_bo(struct brw_context *brw, - drm_intel_bo *bo, + brw_bo *bo, mesa_format format, uint32_t offset, uint32_t width, @@ -791,7 +791,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, void intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, struct intel_renderbuffer *irb, - drm_intel_bo *bo, + brw_bo *bo, uint32_t width, uint32_t height, uint32_t pitch) { @@ -2066,7 +2066,7 @@ intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt) */ intel_miptree_resolve_color(brw, mt); - drm_intel_bo *bo = mt->bo; + brw_bo *bo = mt->bo; if (drm_intel_bo_references(brw->batch.bo, bo)) intel_batchbuffer_flush(brw); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 790d312..641ccbb 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -33,7 +33,7 @@ * The hardware has a fixed layout of a texture depending on parameters such * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of * mipmap levels. The individual level/layer slices are each 2D rectangles of - * pixels at some x/y offset from the start of the drm_intel_bo. + * pixels at some x/y offset from the start of the brw_bo. * * Original OpenGL allowed texture miplevels to be specified in arbitrary * order, and a texture may change size over time. Thus, each @@ -53,6 +53,8 @@ #include "intel_resolve_map.h" #include <GL/internal/dri_interface.h> +#include "brw_batch.h" + #ifdef __cplusplus extern "C" { #endif @@ -321,7 +323,7 @@ enum miptree_array_layout { struct intel_miptree_aux_buffer { /** Buffer object containing the pixel data. */ - drm_intel_bo *bo; + brw_bo *bo; uint32_t pitch; /**< pitch in bytes. */ @@ -340,7 +342,7 @@ enum intel_miptree_tr_mode { struct intel_mipmap_tree { /** Buffer object containing the pixel data. */ - drm_intel_bo *bo; + brw_bo *bo; uint32_t pitch; /**< pitch in bytes. */ @@ -555,7 +557,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, struct intel_mipmap_tree * intel_miptree_create_for_bo(struct brw_context *brw, - drm_intel_bo *bo, + brw_bo *bo, mesa_format format, uint32_t offset, uint32_t width, @@ -567,7 +569,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, void intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, struct intel_renderbuffer *irb, - drm_intel_bo *bo, + brw_bo *bo, uint32_t width, uint32_t height, uint32_t pitch); diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c index 6c6bd86..d452046 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c @@ -60,7 +60,7 @@ do_blit_drawpixels(struct gl_context * ctx, struct brw_context *brw = brw_context(ctx); struct intel_buffer_object *src = intel_buffer_object(unpack->BufferObj); GLuint src_offset; - drm_intel_bo *src_buffer; + brw_bo *src_buffer; DBG("%s\n", __func__); diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index 6bc36de..f1f585f 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -84,7 +84,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, int dst_pitch; /* The miptree's buffer. */ - drm_intel_bo *bo; + brw_bo *bo; int error = 0; diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h index e054b69..b5bbc1e 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.h +++ b/src/mesa/drivers/dri/i965/intel_screen.h @@ -44,6 +44,9 @@ struct intel_screen int deviceID; const struct brw_device_info *devinfo; + dri_bufmgr *bufmgr; + drm_intel_bo *workaround_bo; + __DRIscreen *driScrnPriv; /* So long as we do not frequently write to these booleans, we can @@ -73,9 +76,6 @@ struct intel_screen #define HW_HAS_PIPELINED_SOL_OFFSET (1<<0) #define HW_HAS_PIPELINED_OACONTROL (1<<1) - dri_bufmgr *bufmgr; - drm_intel_bo *workaround_bo; - /** * A unique ID for shader programs. */ diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c b/src/mesa/drivers/dri/i965/intel_syncobj.c index 3849e2e..36fafd0 100644 --- a/src/mesa/drivers/dri/i965/intel_syncobj.c +++ b/src/mesa/drivers/dri/i965/intel_syncobj.c @@ -45,7 +45,7 @@ struct brw_fence { /** The fence waits for completion of this batch. */ - drm_intel_bo *batch_bo; + brw_bo *batch_bo; bool signalled; }; diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index e16b0de..04815c6 100644 --- a/src/mesa/drivers/dri/i965/intel_tex.c +++ b/src/mesa/drivers/dri/i965/intel_tex.c @@ -330,9 +330,9 @@ intel_set_texture_storage_for_buffer_object(struct gl_context *ctx, assert(intel_texobj->mt == NULL); - drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj, - buffer_offset, - row_stride * image->Height); + brw_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj, + buffer_offset, + row_stride * image->Height); intel_texobj->mt = intel_miptree_create_for_bo(brw, bo, image->TexFormat, diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 7007490..8b2ec0f 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -144,7 +144,7 @@ intelTexImage(struct gl_context * ctx, static void intel_set_texture_image_bo(struct gl_context *ctx, struct gl_texture_image *image, - drm_intel_bo *bo, + brw_bo *bo, GLenum target, GLenum internalFormat, mesa_format format, @@ -367,7 +367,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, int dst_pitch; /* The miptree's buffer. */ - drm_intel_bo *bo; + brw_bo *bo; int error = 0; diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index a688007..c771af9 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -86,7 +86,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, int src_pitch; /* The miptree's buffer. */ - drm_intel_bo *bo; + brw_bo *bo; int error = 0; diff --git a/src/mesa/drivers/dri/i965/intel_upload.c b/src/mesa/drivers/dri/i965/intel_upload.c index 308f210..2324a2c 100644 --- a/src/mesa/drivers/dri/i965/intel_upload.c +++ b/src/mesa/drivers/dri/i965/intel_upload.c @@ -88,7 +88,7 @@ void * intel_upload_space(struct brw_context *brw, uint32_t size, uint32_t alignment, - drm_intel_bo **out_bo, + brw_bo **out_bo, uint32_t *out_offset) { uint32_t offset; @@ -130,7 +130,7 @@ intel_upload_data(struct brw_context *brw, const void *data, uint32_t size, uint32_t alignment, - drm_intel_bo **out_bo, + brw_bo **out_bo, uint32_t *out_offset) { void *dst = intel_upload_space(brw, size, alignment, out_bo, out_offset); -- 2.5.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev