Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 53f7698..9a3c844 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -40,8 +40,7 @@ #define FILE_DEBUG_FLAG DEBUG_MIPTREE static unsigned int -tr_mode_horizontal_texture_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt) +tr_mode_horizontal_texture_alignment(const struct intel_mipmap_tree *mt) { const unsigned *align_yf; const unsigned bpp = _mesa_get_format_bytes(mt->format) * 8; @@ -58,6 +57,8 @@ tr_mode_horizontal_texture_alignment(const struct brw_context *brw, const unsigned align_3d_yf[] = {16, 8, 8, 8, 4}; int i = 0; + assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE); + /* Alignment computations below assume bpp >= 8 and a power of 2. */ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)); @@ -166,7 +167,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw, return 8; if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) { - uint32_t align = tr_mode_horizontal_texture_alignment(brw, mt); + uint32_t align = tr_mode_horizontal_texture_alignment(mt); /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32. */ return align < 32 ? 32 : align; } @@ -178,8 +179,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw, } static unsigned int -tr_mode_vertical_texture_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt) +tr_mode_vertical_texture_alignment(const struct intel_mipmap_tree *mt) { const unsigned *align_yf; const unsigned bpp = _mesa_get_format_bytes(mt->format) * 8; @@ -190,7 +190,7 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw, const unsigned align_3d_yf[] = {16, 16, 16, 8, 8}; int i = 0; - assert(brw->gen >= 9); + assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE); /* Alignment computations below assume bpp >= 8 and a power of 2. */ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ; @@ -278,7 +278,7 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw, if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE && mt->target != GL_TEXTURE_1D && mt->target != GL_TEXTURE_1D_ARRAY) { - uint32_t align = tr_mode_vertical_texture_alignment(brw, mt); + uint32_t align = tr_mode_vertical_texture_alignment(mt); /* XY_FAST_COPY_BLT doesn't support vertical alignment < 64 */ return align < 64 ? 64 : align; } -- 2.4.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev