On Wed, Aug 26, 2015 at 10:52:58AM -0700, Ben Widawsky wrote:
> Docs suggest this is no longer required starting with Gen8.
>
> Perf (no regressions in n=20)
> OglMultithread 0.67%
> OglTerrainPanInst 0.12%
> trex 0.45%
> warsow 0.64%
I forgot to mention this data is from BDW GT3
>
> I have a couple of spurious failures in piglit on BSW, and SKL. I have no
> evidence that they are related to this patch.
>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
> src/mesa/drivers/dri/i965/brw_pipe_control.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 7ee3cb6..a2aef8a 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -193,6 +193,14 @@ brw_emit_depth_stall_flushes(struct brw_context *brw)
> {
> assert(brw->gen >= 6 && brw->gen <= 9);
>
> + /* Starting on BDW, these pipe controls are unnecessary.
> + *
> + * WM HW will internally manage the draining pipe and flushing of the
> caches
> + * when this command is issued. The PIPE_CONTROL restrictions are
> removed.
> + */
> + if (brw->gen >= 8)
> + return;
> +
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
> --
> 2.5.0
>
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