On Thu, 2015-11-19 at 10:54 -0500, Connor Abbott wrote: > On Thu, Nov 19, 2015 at 5:05 AM, Iago Toral Quiroga <ito...@igalia.com> wrote: > > These patches are fixes extracted from Connor's fp64 branch that > > I would like to review and land ahead of the rest. They are > > independent of the rest of the series, some of them are even > > general fixes unrelated to fp64 that could fix issues in master, > > others are fairly trivial and we can easily land them now. > > > > It will help reduce the size of a rather big series (115 patches > > and counting) that is still in development and ease future > > rebases a little, specially since there is a patch that renames > > one of the nir types, so we probably want to land that soon. > > > > Apparently, Connor sent most of these for review back in August but > > they did not get reviewed back then. I went ahead and added my Rb to > > all but one: > > > > i965/fs: add stride restrictions for copy propagation > > > > I could not verify all the conditions (particularly, the cases where we > > allow > > 0 strides), so it would be nice if someone else could review that or point > > me > > to the place in the docs where it says that 0 strides are safe for these > > situations. Comments/Reviews to the other patches are also welcome :) > > Well, the docs don't say that it's unsafe either :) But more > seriously, we use 0 strides all the time -- in particular, we use them > for uniforms when they get promoted to push constants, since when > they're pushed to the EU they're packed into registers with, say, 8 > 32-bit things per SIMD8 register. So to get, say, the second uniform, > we need to say "get the second channel of this register and splat it > to all the channels of the source," which we can do with a source of > stride 0 and offset 1.
Yes, that is what we do with set_smear(), right. Only Haswell has an absolute statement saying that stride must be 1 for Math instructions and we respect that in the patch, it makes sense. Thanks for the clarification. Iago > > > > No piglit regressions on IVB. > > > > Connor Abbott (8): > > i965/fs: print non-1 strides when dumping instructions > > i965/fs: print writemask_all when it's enabled > > i965: fix 64-bit immediates in brw_inst(_set)_bits > > i965/fs: respect force_sechalf/force_writemask_all in CSE > > i965/fs: don't propagate cmod when the exec sizes differ > > i965/fs: add stride restrictions for copy propagation > > i965/vec4: avoid dependency control around Align1 instructions > > nir/builder: only read meaningful channels in nir_swizzle() > > > > Jason Ekstrand (1): > > nir: s/nir_type_unsigned/nir_type_uint > > > > src/gallium/auxiliary/nir/tgsi_to_nir.c | 2 +- > > src/glsl/nir/glsl_to_nir.cpp | 2 +- > > src/glsl/nir/nir.h | 2 +- > > src/glsl/nir/nir_builder.h | 2 +- > > src/glsl/nir/nir_constant_expressions.py | 2 +- > > src/glsl/nir/nir_opcodes.py | 78 > > +++++++++++----------- > > src/glsl/nir/nir_search.c | 4 +- > > src/mesa/drivers/dri/i965/brw_fs.cpp | 15 +++++ > > .../drivers/dri/i965/brw_fs_cmod_propagation.cpp | 3 + > > .../drivers/dri/i965/brw_fs_copy_propagation.cpp | 58 +++++++++++++++- > > src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 + > > src/mesa/drivers/dri/i965/brw_inst.h | 6 +- > > src/mesa/drivers/dri/i965/brw_nir.c | 4 +- > > src/mesa/drivers/dri/i965/brw_vec4.cpp | 17 +++-- > > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 2 +- > > 15 files changed, 142 insertions(+), 57 deletions(-) > > > > -- > > 1.9.1 > > > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev