Hi Mike, Thank you for your reply.
I have created a pull request (link <https://github.com/Xilinx/meta-xilinx/pull/24>) fixing the issue. I hope the patch will be moved to rel2020.1 as well. The current workaround is to define DEFAULTTUNE="cortexa53" in one's configuration. Regards, Adrian On 05.08.2020 19:17, Mike Looijmans wrote: > This is just broken in the meta-xilinx layer. > > It should be either "a72" or "a53", there's no Xilinx chip that > carries both in a single chip. For the MPSoC machines, "a53" is the > correct answer. > > > Met vriendelijke groet / kind regards, > > Mike Looijmans > System Expert > > > TOPIC Embedded Products B.V. > Materiaalweg 4, 5681 RJ Best > The Netherlands > > T: +31 (0) 499 33 69 69 > E: [email protected] > W: www.topicproducts.com > > Please consider the environment before printing this e-mail > On 05-08-2020 18:37, Adrian via lists.yoctoproject.org wrote: >> Hi, >> Due to bug in Vivado v2019.1 I need to move my toolchain to the latest >> Vivado v2020.1 including my yocto toolchain (upgrading from zeus). >> >> I understand I should use branch rel-v2020.1 from meta-xilinx. According >> to its configuration, it depends on poky in 'zeus' version. However, >> already at the beginning I get an error that >> 'conf/machine/include/tune-cortexa72-cortexa53.inc' included by >> '/meta-xilinx-bsp/conf/machine/include/soc-tune-include.inc' doesn't >> exist. >> >> In fact, I can find 'tune-cortexa72-cortexa53.inc' it in 'dunfell' >> version of poky, not 'zeus'. >> >> What is the correct dependency of rel-v2010.1 then? Is it a stable >> version supporting Vivado v2020.1? >> >> Regards, >> >> Adrian >> >> >> >> > > > >
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