Am Fri, Apr 02, 2021 at 12:56:24PM +1100 schrieb Darren Tucker: > On Fri, Apr 02, 2021 at 01:01:30AM +0200, Mark Kettenis wrote: > > Hi Darren, > > > > This got broken when Patrick fixed something related to slow mode for > > the Marvel ARMADA 8040 SoC. The diff below fixes it for me on my > > Turris MOX which uses the same SoC. Not entirely sure what is going > > wrong here since looking at the Linux code suggests that Patrick's fix > > should work on the ARMADA 3720 as well. > > Confirmed that this fixes it. dmesg at end of mail.
Damn. I'm sorry, it wasn't my intention to break anything with that. As far as I remember, that particular change was an attempt to reduce diff. This one wasn't even needed to fix my ClearFog GT8K. By the way, U-Boot always sets slow mode for legacy and high speed, which is similar to what we had before. I would actually propose reverting my change completely. My GT 8K still works, but even better: it seems to make the SD card show up on my early revision MacchiatoBin. -sdmmc1: can't enable card scsibus2 at sdmmc0: 2 targets, initiator 0 sd1 at scsibus2 targ 1 lun 0: <Samsung, 8GME4R, 0000> removable sd1: 7456MB, 512 bytes/sector, 15269888 sectors +scsibus3 at sdmmc1: 2 targets, initiator 0 +sd2 at scsibus3 targ 1 lun 0: <SD/MMC, 00000, 0000> removable +sd2: 7632MB, 512 bytes/sector, 15630336 sectors Maybe you both can try my revert and make sure it doesn't introduce any other regressions? > > That BRUME thingy looks cute, but has a bit of an issue. It doesn't > > really have three Ethernet ports. Instead those ports are part of a > > switch that also connects to an Ethernet interface on the SoC. > > Yeah I noticed that. Single ethernet plus programmable switch seems to > be pretty common in this class of device. And if someone wants to program it, feel free to, mvsw(4) exists for a reason, might just need some code. :) diff --git a/sys/dev/fdt/sdhc_fdt.c b/sys/dev/fdt/sdhc_fdt.c index 56bf15c46fa..cc0239df682 100644 --- a/sys/dev/fdt/sdhc_fdt.c +++ b/sys/dev/fdt/sdhc_fdt.c @@ -430,8 +430,8 @@ phy_init: XENON_EMMC_PHY_TIMING_ADJUST); reg |= XENON_EMMC_PHY_TIMING_ADJUST_SAMPL_INV_QSP_PHASE_SELECT; reg &= ~XENON_EMMC_PHY_TIMING_ADJUST_SLOW_MODE; - if ((timing == SDMMC_TIMING_LEGACY || - timing == SDMMC_TIMING_HIGHSPEED) && sc->sc_slow_mode) + if (timing == SDMMC_TIMING_LEGACY || + timing == SDMMC_TIMING_HIGHSPEED || sc->sc_slow_mode) reg |= XENON_EMMC_PHY_TIMING_ADJUST_SLOW_MODE; bus_space_write_4(sc->sc_iot, sc->sc_ioh, XENON_EMMC_PHY_TIMING_ADJUST, reg);