Theo de Raadt:
> That was in 2022. Lots of people will have machines without new BIOS.
I have the latest firmware and the ccp(4) RNG returns nothing but 0.
> I wonder if our kernel should have similar code to enable the registers.
I tried that yesterday to no effect... but I'm not certain that
what I'm trying to do below is equivalent to this coreboot change:
+ /* Enable access to PSP MMIO BARs. This is needed for CCP. */
+ dev = pcidev_on_root(8, 0);
+ if (dev != NULL)
+ pci_update_config8(dev, 0x48, 0xff, 0x3d);
# pcidump 0:8:0
0:8:0: AMD 16h Crypto
Index: dev/pci/ccp_pci.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/ccp_pci.c,v
retrieving revision 1.7
diff -u -p -r1.7 ccp_pci.c
--- dev/pci/ccp_pci.c 24 Oct 2022 04:57:29 -0000 1.7
+++ dev/pci/ccp_pci.c 22 Apr 2023 21:52:32 -0000
@@ -31,7 +31,8 @@
#include <dev/ic/ccpvar.h>
-#define CCP_PCI_BAR 0x18
+#define CCP_PCI_BAR 0x18
+#define CCP_PSP_BAR_ENABLES 0x48
int ccp_pci_match(struct device *, void *, void *);
void ccp_pci_attach(struct device *, struct device *, void *);
@@ -62,7 +63,8 @@ ccp_pci_attach(struct device *parent, st
{
struct ccp_softc *sc = (struct ccp_softc *)self;
struct pci_attach_args *pa = aux;
- pcireg_t memtype;
+ pci_chipset_tag_t pc = pa->pa_pc;
+ pcireg_t memtype, reg;
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, CCP_PCI_BAR);
if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) {
@@ -75,6 +77,10 @@ ccp_pci_attach(struct device *parent, st
printf(": cannot map registers\n");
return;
}
+
+ reg = pci_conf_read(pc, pa->pa_tag, CCP_PSP_BAR_ENABLES);
+ reg |= 0x3d;
+ pci_conf_write(pc, pa->pa_tag, CCP_PSP_BAR_ENABLES, reg);
ccp_attach(sc);
}
--
Christian "naddy" Weisgerber [email protected]
