On Sun, Oct 01, 2006 at 05:59:20PM -0400, [EMAIL PROTECTED] wrote:
> I have done some preliminary poking around, what I have learned so far is
> that the celeron processor can be paired with the ich southbridges that
> support speedstep, it however dosen't actually support this functionality.
> I have a patch in the works that will ensure that we only attempt to use
> ich speedstep on pentium 4 cpu's, in which case you wont have this
> setperf method, but you should still have p4tcc clock throttling.
> gwk
to be hones, i'm aware that my cpu doesn't do speedstep, if it did i
would probably see something like (epsecially the last line):
cpu0: Intel(R) Pentium(R) M processor 1.40GHz ("GenuineIntel" 686-class) 1.40
GHz
cpu0:
FPU,V86,DE,PSE,TSC,MSR,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,TM,SBF,EST,TM2
cpu0: Enhanced SpeedStep 1400 MHz (1116 mV): speeds: 1400, 1300, 1200, 1100,
1000, 900, 800, 600 MHz
in my dmesg.. so that's not the problem.. what i wanted to know is
wheather the hw.cpuspeed is set correctly (even before playing with setperf),
and if it's not (which looks like that way) wheather it is important enough
to fill in a bug report..
the second thing (setperf issues) was purly informative. what you've
written about it seems to explain why it might happen, thanks.
i'd be happy to test your patch.
--
Przemyslaw Nowaczyk <[EMAIL PROTECTED]>
CS student @ Poznan University of Technology
http://unixlab.cs.put.poznan.pl/~inf73015/
