Hello, I was talking to a group doing an implementation of RISC-V, and they had some ideas about on-chip coprocessors like ML, e.g.
What would it take to get MIT/Scheme into Si? Alternatively, I was thinking it would be great to have a RISC-V port. Thank you for any ideas. -- Stewart Milberger ^|||^ \. ./ Scheming | | Pony { }