Module update for Verilog::Pli

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Record update in the PAUSE modules database:

       modid: [Verilog::Pli]
       statd: [R]
       stats: [d]
       statl: [c]
       stati: [h]
       statp: [p] was [?]
 description: [Access to simulator functions]
      userid: [WSNYDER]
   chapterid: [ 9]
    mlstatus: [list]

Data entered by Wilson Snyder (WSNYDER).
Please check if they are correct.

The Pause