The following module was proposed for inclusion in the Module List:
modid: Verilog::Netlist
DSLIP: RdpOp
description: Build and access netlist interconnects
userid: WSNYDER (Wilson Snyder)
chapterid: 9 (Language_Interfaces)
communities:
similar:
rationale:
This is a higher level abstraction of the Verilog modules, allowing
extraction of netlist information at a higher level then other
previous methods.
It's also the baseclass for the listed SystemC::Netlist.
enteredby: WSNYDER (Wilson Snyder)
enteredon: Mon Apr 8 14:04:15 2002 GMT
The resulting entry would be:
Verilog::
::Netlist RdpOp Build and access netlist interconnects WSNYDER
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