Author: zoltan
Date: 2008-02-05 16:40:06 -0500 (Tue, 05 Feb 2008)
New Revision: 94960
Modified:
branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog
branches/vargaz/mini-linear-il/mono/mono/mini/cpu-arm.md
branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md
branches/vargaz/mini-linear-il/mono/mono/mini/cpu-sparc.md
branches/vargaz/mini-linear-il/mono/mono/mini/cpu-x86.md
branches/vargaz/mini-linear-il/mono/mono/mini/generics-variant-types.2.il
branches/vargaz/mini-linear-il/mono/mono/mini/inssel-x86.brg
branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h
branches/vargaz/mini-linear-il/mono/mono/mini/mini-arm.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini-sparc.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini-x86.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini.c
Log:
2008-02-05 Zoltan Varga <[EMAIL PROTECTED]>
* cpu-<ARCH>.md mini-<ARCH>.md: Get rid of CEE_ opcodes.
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog 2008-02-05
21:40:06 UTC (rev 94960)
@@ -1,5 +1,7 @@
2008-02-05 Zoltan Varga <[EMAIL PROTECTED]>
+ * cpu-<ARCH>.md mini-<ARCH>.md: Get rid of CEE_ opcodes.
+
* cpu-amd64.md mini-amd64.c: Remove unused opcodes.
* mini.c (mono_normalize_opcodes): New pass to get rid of CEE_ opcodes.
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/cpu-arm.md
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/cpu-arm.md 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/cpu-arm.md 2008-02-05
21:40:06 UTC (rev 94960)
@@ -43,7 +43,7 @@
#
# See the code in mini-x86.c for more details on how the specifiers are used.
#
-label:
+label: len:0
nop: len:0
dummy_use: len:0
dummy_store: len:0
@@ -52,21 +52,9 @@
memory_barrier: len:4
break: len:32
jmp: len:92
-call: dest:a clob:c len:20
br: len:4
br_reg: src1:i len:8
-beq: len:8
-bge: len:8
-bgt: len:8
-ble: len:8
-blt: len:8
-bne.un: len:8
-bge.un: len:8
-bgt.un: len:8
-ble.un: len:8
-blt.un: len:8
-
int_beq: len:8
int_bge: len:8
int_bgt: len:8
@@ -95,34 +83,6 @@
stind.r4: src1:b src2:f
stind.r8: src1:b src2:f
-add: dest:i src1:i src2:i len:4
-sub: dest:i src1:i src2:i len:4
-mul: dest:i src1:i src2:i len:4
-div: dest:i src1:i src2:i len:40
-div.un: dest:i src1:i src2:i len:16
-rem: dest:i src1:i src2:i len:48
-rem.un: dest:i src1:i src2:i len:24
-and: dest:i src1:i src2:i len:4
-or: dest:i src1:i src2:i len:4
-xor: dest:i src1:i src2:i len:4
-shl: dest:i src1:i src2:i len:4
-shr: dest:i src1:i src2:i len:4
-shr.un: dest:i src1:i src2:i len:4
-
-neg: dest:i src1:i len:4
-not: dest:i src1:i len:4
-conv.i1: dest:i src1:i len:8
-conv.i2: dest:i src1:i len:8
-conv.i4: dest:i src1:i len:4
-conv.r4: dest:f src1:i len:36
-conv.r8: dest:f src1:i len:36
-conv.u4: dest:i src1:i
-conv.r.un: dest:f src1:i len:56
-
-conv.u2: dest:i src1:i len:8
-conv.u1: dest:i src1:i len:4
-conv.i: dest:i src1:i len:4
-
int_add: dest:i src1:i src2:i len:4
int_sub: dest:i src1:i src2:i len:4
int_mul: dest:i src1:i src2:i len:4
@@ -212,6 +172,8 @@
checkthis: src1:b len:4
call: dest:a clob:c len:20
+call_reg: dest:a src1:i len:8 clob:c
+call_membase: dest:a src1:b len:12 clob:c
voidcall: len:20 clob:c
voidcall_reg: src1:i len:8 clob:c
voidcall_membase: src1:b len:12 clob:c
@@ -221,24 +183,16 @@
lcall: dest:l len:20 clob:c
lcall_reg: dest:l src1:i len:8 clob:c
lcall_membase: dest:l src1:b len:12 clob:c
-
vcall: len:20 clob:c
vcall_reg: src1:i len:8 clob:c
vcall_membase: src1:b len:12 clob:c
-
vcall2: len:20 clob:c
vcall2_reg: src1:i len:8 clob:c
vcall2_membase: src1:b len:12 clob:c
-call_reg: dest:a src1:i len:8 clob:c
-call_membase: dest:a src1:b len:12 clob:c
iconst: dest:i len:16
r4const: dest:f len:20
r8const: dest:f len:20
-<<<<<<< .working
-=======
-label: len:0
->>>>>>> .merge-right.r94008
store_membase_imm: dest:b len:20
store_membase_reg: dest:b src1:i len:20
storei1_membase_imm: dest:b len:20
@@ -324,7 +278,6 @@
cond_exc_no: len:8
cond_exc_c: len:12
cond_exc_nc: len:8
-<<<<<<< .working
cond_exc_ieq: len:8
cond_exc_ine_un: len:8
@@ -341,27 +294,10 @@
cond_exc_ic: len:12
cond_exc_inc: len:8
-=======
->>>>>>> .merge-right.r94008
long_conv_to_ovf_i: dest:i src1:i src2:i len:30
-<<<<<<< .working
long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:30
-=======
->>>>>>> .merge-right.r94008
-long_mul_ovf:
long_conv_to_r_un: dest:f src1:i src2:i len:37
-<<<<<<< .working
-float_beq: len:20
-float_bne_un: len:20
-float_blt: len:20
-float_blt_un: len:20
-float_bgt: len:20
-float_bgt_un: len:20
-float_bge: len:20
-float_bge_un: len:20
-float_ble: len:20
-float_ble_un: len:20
-=======
+
float_beq: src1:f src2:f len:20
float_bne_un: src1:f src2:f len:20
float_blt: src1:f src2:f len:20
@@ -372,7 +308,7 @@
float_bge_un: src1:f src2:f len:20
float_ble: src1:f src2:f len:20
float_ble_un: src1:f src2:f len:20
->>>>>>> .merge-right.r94008
+
float_add: dest:f src1:f src2:f len:4
float_sub: dest:f src1:f src2:f len:4
float_mul: dest:f src1:f src2:f len:4
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md 2008-02-05
21:40:06 UTC (rev 94960)
@@ -16,31 +16,6 @@
not_reached: len:0
not_null: src1:i len:0
-beq: len:48
-bge: len:48
-bgt: len:48
-ble: len:48
-blt: len:48
-bne.un: len:48
-bge.un: len:48
-bgt.un: len:48
-ble.un: len:48
-blt.un: len:48
-
-add: dest:i src1:i src2:i len:48
-sub: dest:i src1:i src2:i len:48
-mul: dest:i src1:i src2:i len:48
-div: dest:a src1:a src2:i len:48 clob:d
-div.un: dest:a src1:a src2:i len:48 clob:d
-rem: dest:d src1:a src2:i len:48 clob:a
-rem.un: dest:d src1:a src2:i len:48 clob:a
-and: dest:i src1:i src2:i len:48
-or: dest:i src1:i src2:i len:48
-xor: dest:i src1:i src2:i len:48
-shl: dest:i src1:i src2:s len:48
-shr: dest:i src1:i src2:s len:48
-shr.un: dest:i src1:i src2:s len:48
-
long_add: dest:i src1:i src2:i len:48
long_sub: dest:i src1:i src2:i len:48
long_and: dest:i src1:i src2:i len:48
@@ -50,17 +25,6 @@
long_shr: dest:i src1:i src2:s len:48
long_shr_un: dest:i src1:i src2:s len:48
-neg: dest:i src1:i len:48
-not: dest:i src1:i len:48
-conv.i1: dest:i src1:i len:48
-conv.i2: dest:i src1:i len:48
-conv.i4: dest:i src1:i len:48
-conv.i8: dest:i src1:i len:48
-conv.r4: dest:f src1:i len:112
-conv.r8: dest:f src1:i len:112
-conv.u4: dest:i src1:i len:112
-conv.u8: dest:i src1:i len:112
-
long_neg: dest:i src1:i len:48
long_not: dest:i src1:i len:48
long_conv_to_i1: dest:i src1:i len:48
@@ -73,21 +37,14 @@
long_conv_to_u8: dest:i src1:i len:112
long_conv_to_r4: dest:f src1:i len:112
long_conv_to_r8: dest:f src1:i len:112
+long_conv_to_r_un: dest:f src1:i len:48
+long_conv_to_ovf_i4_un: dest:i src1:i len:96
+long_conv_to_ovf_u4: dest:i src1:i len:48
-conv.r.un: dest:f src1:i len:48
throw: src1:i len:96
rethrow: src1:i len:48
-conv.ovf.i4.un: dest:i src1:i len:96
-conv.ovf.u4.un:
-conv.ovf.u4: dest:i src1:i len:48
ckfinite: dest:f src1:f len:48
-conv.u2: dest:i src1:i len:48
-conv.u1: dest:i src1:i len:48
-conv.i: dest:i src1:i len:48
-mul.ovf: dest:i src1:i src2:i len:48
-# this opcode is handled specially in the code generator
-mul.ovf.un: dest:i src1:i src2:i len:48
-conv.u: dest:i src1:i len:48
+
ceq: dest:c len:48
cgt: dest:c len:48
cgt.un: dest:c len:48
@@ -108,7 +65,10 @@
setret: dest:r src1:i len:48
setlret: dest:r src1:i src2:i len:48
checkthis: src1:b len:48
+
call: dest:r clob:c len:80
+call_reg: dest:r src1:i len:80 clob:c
+call_membase: dest:r src1:b len:80 clob:c
voidcall: clob:c len:80
voidcall_reg: src1:i clob:c len:80
voidcall_membase: src1:b clob:c len:80
@@ -124,8 +84,7 @@
vcall2: len:80 clob:c
vcall2_reg: src1:i len:80 clob:c
vcall2_membase: src1:b len:80 clob:c
-call_reg: dest:r src1:i len:80 clob:c
-call_membase: dest:r src1:b len:80 clob:c
+
iconst: dest:i len:48
i8const: dest:i len:48
r4const: dest:f len:48
@@ -243,10 +202,12 @@
float_clt_un_membase: dest:i src1:f src2:b len:48
float_conv_to_u: dest:i src1:f len:48
fmove: dest:f src1:f len:48
+
call_handler: len:96
start_handler: len:96
endfilter: len:96
endfinally: len:96
+
aot_const: dest:i len:48
tls_get: dest:i len:48
atomic_add_i4: src1:b src2:i dest:i len:48
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/cpu-sparc.md
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/cpu-sparc.md 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/cpu-sparc.md 2008-02-05
21:40:06 UTC (rev 94960)
@@ -60,16 +60,6 @@
not_reached: len:0
not_null: src1:i len:0
-beq: len:8
-bge: len:8
-bgt: len:8
-ble: len:8
-blt: len:8
-bne.un: len:64
-bge.un: len:64
-bgt.un: len:64
-ble.un: len:64
-blt.un: len:64
sparc_brz: src1:i len: 8
sparc_brlez: src1:i len: 8
sparc_brlz: src1:i len: 8
@@ -97,47 +87,18 @@
stind.r4: src1:b src2:f
stind.r8: src1:b src2:f
-add: dest:i src1:i src2:i len:64
-sub: dest:i src1:i src2:i len:4
-mul: dest:i src1:i src2:i len:4
-div: dest:i src1:i src2:i len:64
-div.un: dest:i src1:i src2:i len:8
-rem: dest:d src1:i src2:i len:64
-rem.un: dest:d src1:i src2:i len:64
-and: dest:i src1:i src2:i len:4
-or: dest:i src1:i src2:i len:4
-xor: dest:i src1:i src2:i len:4
-shl: dest:i src1:i src2:i len:4
-shr: dest:i src1:i src2:i len:4
-shr.un: dest:i src1:i src2:i len:4
-neg: dest:i src1:i len:4
-not: dest:i src1:i len:4
-conv.i1: dest:i src1:i len:8
-conv.i2: dest:i src1:i len:8
-conv.i4: dest:i src1:i len:4
-conv.i8: dest:i src1:i len:4
-conv.r4: dest:f src1:i len:64
-conv.r8: dest:f src1:i len:64
-conv.u4: dest:i src1:i len:4
-conv.u8: dest:i src1:i len:4
-conv.u2: dest:i src1:i len:8
-conv.u1: dest:i src1:i len:4
-conv.i: dest:i src1:i len:4
-
throw: src1:i len:64
rethrow: src1:i len:64
+start_handler: len:64
+endfinally: len:64
+endfilter: src1:i len:64
+call_handler: len:64
+
conv.ovf.u4: dest:i src1:i len:64
ckfinite: dest:f src1:f len:40
-mul.ovf: dest:i src1:i src2:i len:64
-mul.ovf.un: dest:i src1:i src2:i len:64
-
int_mul_ovf: dest:i src1:i src2:i len:64
int_mul_ovf_un: dest:i src1:i src2:i len:64
-
-start_handler: len:64
-endfinally: len:64
-endfilter: src1:i len:64
conv.u: dest:i src1:i len:4
arglist: src1:i
ceq: dest:i len:64
@@ -304,7 +265,6 @@
float_clt: dest:i src1:f src2:f len:64
float_clt_un: dest:i src1:f src2:f len:64
float_conv_to_u: dest:i src1:f len:64
-call_handler: len:64
aot_const: dest:i len:64
adc: dest:i src1:i src2:i len:4
addcc: dest:i src1:i src2:i len:4
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/cpu-x86.md
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/cpu-x86.md 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/cpu-x86.md 2008-02-05
21:40:06 UTC (rev 94960)
@@ -63,19 +63,8 @@
not_null: src1:i len:0
break: len:1
jmp: len:32
-call: dest:a clob:c len:17
ret: len:1
br: len:5
-beq: len:6
-bge: len:6
-bgt: len:6
-ble: len:6
-blt: len:6
-bne.un: len:6
-bge.un: len:6
-bgt.un: len:6
-ble.un: len:6
-blt.un: len:6
int_beq: len:6
int_bge: len:6
@@ -104,32 +93,6 @@
stind.r4: dest:f src1:b
stind.r8: dest:f src1:b
-add: dest:i src1:i src2:i len:2 clob:1
-sub: dest:i src1:i src2:i len:2 clob:1
-mul: dest:i src1:i src2:i len:3 clob:1
-div: dest:a src1:a src2:i len:15 clob:d
-div.un: dest:a src1:a src2:i len:15 clob:d
-rem: dest:d src1:a src2:i len:15 clob:a
-rem.un: dest:d src1:a src2:i len:15 clob:a
-and: dest:i src1:i src2:i len:2 clob:1
-or: dest:i src1:i src2:i len:2 clob:1
-xor: dest:i src1:i src2:i len:2 clob:1
-shl: dest:i src1:i src2:s clob:1 len:2
-shr: dest:i src1:i src2:s clob:1 len:2
-shr.un: dest:i src1:i src2:s clob:1 len:2
-
-neg: dest:i src1:i len:2 clob:1
-not: dest:i src1:i len:2 clob:1
-conv.i1: dest:i src1:y len:3
-conv.i2: dest:i src1:i len:3
-conv.i4: dest:i src1:i len:2
-conv.r4: dest:f src1:i len:7
-conv.r8: dest:f src1:i len:7
-conv.u4: dest:i src1:i
-conv.u2: dest:i src1:i len:3
-conv.u1: dest:i src1:y len:3
-conv.i: dest:i src1:i len:3
-
int_add: dest:i src1:i src2:i len:2 clob:1
int_sub: dest:i src1:i src2:i len:2 clob:1
int_mul: dest:i src1:i src2:i len:3 clob:1
@@ -163,12 +126,10 @@
start_handler: len:16
endfinally: len:16
endfilter: src1:a len:16
+call_handler: len:10
ckfinite: dest:f src1:f len:32
-mul.ovf: dest:i src1:i src2:i clob:1 len:9
-mul.ovf.un: dest:i src1:i src2:i len:16
-
int_mul_ovf: dest:i src1:i src2:i clob:1 len:9
int_mul_ovf_un: dest:i src1:i src2:i len:16
@@ -199,6 +160,10 @@
setret: dest:a src1:i len:2
setlret: dest:l src1:i src2:i len:4
checkthis: src1:b len:2
+
+call: dest:a clob:c len:17
+call_reg: dest:a src1:i len:11 clob:c
+call_membase: dest:a src1:b len:16 clob:c
voidcall: len:17 clob:c
voidcall_reg: src1:i len:11 clob:c
voidcall_membase: src1:b len:16 clob:c
@@ -208,17 +173,13 @@
lcall: dest:l len:17 clob:c
lcall_reg: dest:l src1:i len:11 clob:c
lcall_membase: dest:l src1:b len:16 clob:c
-
vcall: len:17 clob:c
vcall_reg: src1:i len:11 clob:c
vcall_membase: src1:b len:16 clob:c
-
vcall2: len:17 clob:c
vcall2_reg: src1:i len:11 clob:c
vcall2_membase: src1:b len:16 clob:c
-call_reg: dest:a src1:i len:11 clob:c
-call_membase: dest:a src1:b len:16 clob:c
iconst: dest:i len:5
r4const: dest:f len:15
r8const: dest:f len:16
@@ -262,7 +223,6 @@
div_imm: dest:a src1:a src2:i len:15 clob:d
div_un_imm: dest:a src1:a src2:i len:15 clob:d
-# This returns EAX
rem_imm: dest:a src1:a src2:i len:15 clob:d
rem_un_imm: dest:d src1:a src2:i len:15 clob:a
and_imm: dest:i src1:i len:6 clob:1
@@ -277,12 +237,8 @@
#int_subcc_imm: dest:i src1:i len:6 clob:1
int_sub_imm: dest:i src1:i len:6 clob:1
int_mul_imm: dest:i src1:i len:9
-# there is no actual support for division or reminder by immediate
-# we simulate them, though (but we need to change the burg rules
-# to allocate a symbolic reg for src2)
int_div_imm: dest:a src1:a len:15 clob:d
int_div_un_imm: dest:a src1:a len:15 clob:d
-# This returns EAX
int_rem_imm: dest:a src1:a len:15 clob:d
int_rem_un_imm: dest:d src1:a len:15 clob:a
int_and_imm: dest:i src1:i len:6 clob:1
@@ -327,7 +283,6 @@
long_shr_un: dest:L src1:L src2:s clob:1 len:22
long_conv_to_ovf_i: dest:i src1:i src2:i len:30
long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:30
-long_mul_ovf:
long_conv_to_r8_2: dest:f src1:i src2:i len:37
long_conv_to_r4_2: dest:f src1:i src2:i len:64
long_conv_to_r_un: dest:f src1:i src2:i len:37
@@ -373,7 +328,6 @@
float_clt: dest:y src1:f src2:f len:25
float_clt_un: dest:y src1:f src2:f len:32
float_conv_to_u: dest:i src1:f len:36
-call_handler: len:10
aot_const: dest:i len:5
jump_table: dest:i len:5
load_gotaddr: dest:i len:64
Modified:
branches/vargaz/mini-linear-il/mono/mono/mini/generics-variant-types.2.il
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/generics-variant-types.2.il
2008-02-05 21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/generics-variant-types.2.il
2008-02-05 21:40:06 UTC (rev 94960)
@@ -21,7 +21,7 @@
//
// A Covariant interface
//
-.class interface public abstract auto ansi beforefieldinit IEnumerator`1<+T>
+.class interface public abstract auto ansi beforefieldinit MyIEnumerator`1<+T>
{
.method public hidebysig abstract virtual instance bool MoveNext() cil
managed
{
@@ -33,7 +33,7 @@
.property !T Current()
{
- .get instance !T IEnumerator`1::get_Current()
+ .get instance !T MyIEnumerator`1::get_Current()
}
}
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/inssel-x86.brg
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/inssel-x86.brg
2008-02-05 21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/inssel-x86.brg
2008-02-05 21:40:06 UTC (rev 94960)
@@ -50,8 +50,12 @@
#
stmt: OP_START_HANDLER,
-stmt: OP_ENDFINALLY,
+stmt: OP_ENDFINALLY {
+ mono_bblock_add_inst (s->cbb, tree);
+}
+
stmt: OP_ENDFILTER (reg) {
+ tree->sreg1 = state->left->reg1;
mono_bblock_add_inst (s->cbb, tree);
}
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h 2008-02-05
21:40:06 UTC (rev 94960)
@@ -279,7 +279,6 @@
#define MONO_ARCH_COMMON_VTABLE_TRAMPOLINE 1
#define MONO_ARCH_HAVE_CMOV_OPS 1
#define MONO_ARCH_HAVE_NOTIFY_PENDING_EXC 1
-#define MONO_ARCH_ENABLE_NORMALIZE_OPCODES 1
#define MONO_ARCH_AOT_SUPPORTED 1
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-arm.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-arm.c 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-arm.c 2008-02-05
21:40:06 UTC (rev 94960)
@@ -1693,7 +1693,7 @@
if (last_ins && (last_ins->opcode ==
OP_STOREI1_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? CEE_CONV_I1 : CEE_CONV_U1;
+ ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
ins->sreg1 = last_ins->sreg1;
}
break;
@@ -1702,12 +1702,10 @@
if (last_ins && (last_ins->opcode ==
OP_STOREI2_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? CEE_CONV_I2 : CEE_CONV_U2;
+ ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
ins->sreg1 = last_ins->sreg1;
}
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
case OP_SETREG:
ins->opcode = OP_MOVE;
@@ -1793,11 +1791,11 @@
{
switch (op) {
case OP_ADD_IMM:
- return CEE_ADD;
+ return OP_IADD;
case OP_SUB_IMM:
- return CEE_SUB;
+ return OP_ISUB;
case OP_AND_IMM:
- return CEE_AND;
+ return OP_IAND;
case OP_COMPARE_IMM:
return OP_COMPARE;
case OP_ICOMPARE_IMM:
@@ -1811,9 +1809,9 @@
case OP_SBB_IMM:
return OP_SBB;
case OP_OR_IMM:
- return CEE_OR;
+ return OP_IOR;
case OP_XOR_IMM:
- return CEE_XOR;
+ return OP_IXOR;
case OP_LOAD_MEMBASE:
return OP_LOAD_MEMINDEX;
case OP_LOADI4_MEMBASE:
@@ -1922,7 +1920,7 @@
temp->inst_c0 = ins->inst_imm;
temp->dreg = mono_regstate_next_int (cfg->rs);
ins->sreg2 = temp->dreg;
- ins->opcode = CEE_MUL;
+ ins->opcode = OP_IMUL;
break;
case OP_LOCALLOC_IMM:
NEW_INS (cfg, temp, OP_ICONST);
@@ -2586,21 +2584,17 @@
g_assert (arm_is_imm8 (ins->inst_offset));
ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg,
ins->inst_offset);
break;
- case CEE_CONV_I1:
case OP_ICONV_TO_I1:
ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
break;
- case CEE_CONV_I2:
case OP_ICONV_TO_I2:
ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
break;
- case CEE_CONV_U1:
case OP_ICONV_TO_U1:
ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
break;
- case CEE_CONV_U2:
case OP_ICONV_TO_U2:
ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
@@ -2638,7 +2632,6 @@
case OP_IADDCC:
ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
- case CEE_ADD:
case OP_IADD:
ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
@@ -2663,22 +2656,18 @@
g_assert (imm8 >= 0);
ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8,
rot_amount);
break;
- case CEE_ADD_OVF:
case OP_IADD_OVF:
ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
//EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE,
PPC_BR_EQ, "OverflowException");
break;
- case CEE_ADD_OVF_UN:
case OP_IADD_OVF_UN:
ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
//EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE,
PPC_BR_EQ, "OverflowException");
break;
- case CEE_SUB_OVF:
case OP_ISUB_OVF:
ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
//EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE,
PPC_BR_EQ, "OverflowException");
break;
- case CEE_SUB_OVF_UN:
case OP_ISUB_OVF_UN:
ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
//EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE,
PPC_BR_EQ, "OverflowException");
@@ -2708,7 +2697,6 @@
g_assert (imm8 >= 0);
ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8,
rot_amount);
break;
- case CEE_SUB:
case OP_ISUB:
ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
@@ -2738,7 +2726,6 @@
g_assert (imm8 >= 0);
ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8,
rot_amount);
break;
- case CEE_AND:
case OP_IAND:
ARM_AND_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
@@ -2748,15 +2735,10 @@
g_assert (imm8 >= 0);
ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8,
rot_amount);
break;
- case CEE_DIV:
- case CEE_DIV_UN:
case OP_DIV_IMM:
- case CEE_REM:
- case CEE_REM_UN:
case OP_REM_IMM:
/* crappy ARM arch doesn't have a DIV instruction */
g_assert_not_reached ();
- case CEE_OR:
case OP_IOR:
ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
@@ -2766,7 +2748,6 @@
g_assert (imm8 >= 0);
ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8,
rot_amount);
break;
- case CEE_XOR:
case OP_IXOR:
ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
@@ -2776,7 +2757,6 @@
g_assert (imm8 >= 0);
ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8,
rot_amount);
break;
- case CEE_SHL:
case OP_ISHL:
ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
@@ -2787,7 +2767,6 @@
else if (ins->dreg != ins->sreg1)
ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
break;
- case CEE_SHR:
case OP_ISHR:
ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
@@ -2805,19 +2784,15 @@
else if (ins->dreg != ins->sreg1)
ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
break;
- case CEE_SHR_UN:
case OP_ISHR_UN:
ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case CEE_NOT:
case OP_INOT:
ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
break;
- case CEE_NEG:
case OP_INEG:
ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
break;
- case CEE_MUL:
case OP_IMUL:
if (ins->dreg == ins->sreg2)
ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
@@ -2827,12 +2802,10 @@
case OP_MUL_IMM:
g_assert_not_reached ();
break;
- case CEE_MUL_OVF:
case OP_IMUL_OVF:
/* FIXME: handle ovf/ sreg2 != dreg */
ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
break;
- case CEE_MUL_OVF_UN:
case OP_IMUL_OVF_UN:
/* FIXME: handle ovf/ sreg2 != dreg */
ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1,
ins->sreg2);
@@ -2851,8 +2824,6 @@
/* Load the value from the GOT */
ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_ICONV_TO_I4:
case OP_ICONV_TO_U4:
case OP_MOVE:
@@ -2919,7 +2890,6 @@
case OP_VCALL:
case OP_VCALL2:
case OP_VOIDCALL:
- case CEE_CALL:
case OP_CALL:
call = (MonoCallInst*)ins;
if (ins->flags & MONO_INST_HAS_METHOD)
@@ -3163,18 +3133,6 @@
case OP_COND_EXC_INO:
/* FIXME: */
break;
- case CEE_BEQ:
- case CEE_BNE_UN:
- case CEE_BLT:
- case CEE_BLT_UN:
- case CEE_BGT:
- case CEE_BGT_UN:
- case CEE_BGE:
- case CEE_BGE_UN:
- case CEE_BLE:
- case CEE_BLE_UN:
- EMIT_COND_BRANCH (ins, ins->opcode - CEE_BEQ);
- break;
case OP_IBEQ:
case OP_IBNE_UN:
case OP_IBLT:
@@ -3243,7 +3201,7 @@
g_assert (arm_is_fpimm8 (ins->inst_offset));
ARM_LDFS (code, ins->dreg, ins->inst_basereg,
ins->inst_offset);
break;
- case CEE_CONV_R_UN: {
+ case OP_ICONV_TO_R_UN: {
int tmpreg;
tmpreg = ins->dreg == 0? 1: 0;
ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
@@ -3269,11 +3227,9 @@
*/
break;
}
- case CEE_CONV_R4:
case OP_ICONV_TO_R4:
ARM_FLTS (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_R8:
case OP_ICONV_TO_R8:
ARM_FLTD (code, ins->dreg, ins->sreg1);
break;
@@ -3323,18 +3279,6 @@
g_assert (arm_is_fpimm8 (ins->inst_offset));
ARM_FLDS (code, ins->dreg, ins->inst_basereg,
ins->inst_offset);
break;
- case CEE_CONV_R_UN: {
- g_assert_not_reached ();
- break;
- }
- case CEE_CONV_R4:
- g_assert_not_reached ();
- //ARM_FLTS (code, ins->dreg, ins->sreg1);
- break;
- case CEE_CONV_R8:
- g_assert_not_reached ();
- //ARM_FLTD (code, ins->dreg, ins->sreg1);
- break;
#endif
case OP_FCONV_TO_I1:
code = emit_float_to_int (cfg, code, ins->dreg,
ins->sreg1, 1, TRUE);
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c 2008-02-05
21:40:06 UTC (rev 94960)
@@ -1666,7 +1666,7 @@
NEW_INS (cfg, temp, OP_I8CONST);
temp->inst_c0 = ins->inst_offset;
temp->dreg = mono_regstate_next_int (cfg->rs);
- NEW_INS (cfg, temp2, CEE_ADD);
+ NEW_INS (cfg, temp2, OP_LADD);
temp2->sreg1 = ins->inst_destbasereg;
temp2->sreg2 = temp->dreg;
temp2->dreg = mono_regstate_next_int (cfg->rs);
@@ -1724,7 +1724,7 @@
NEW_INS (cfg, temp, OP_I8CONST);
temp->inst_c0 = ins->inst_offset;
temp->dreg = mono_regstate_next_int (cfg->rs);
- NEW_INS (cfg, temp2, CEE_ADD);
+ NEW_INS (cfg, temp2, OP_LADD);
temp2->sreg1 = ins->inst_destbasereg;
temp2->sreg2 = temp->dreg;
temp2->dreg = mono_regstate_next_int (cfg->rs);
@@ -1763,7 +1763,7 @@
NEW_INS (cfg, temp, OP_I8CONST);
temp->inst_c0 = ins->inst_offset;
temp->dreg = mono_regstate_next_int (cfg->rs);
- NEW_INS (cfg, temp2, CEE_ADD);
+ NEW_INS (cfg, temp2, OP_LADD);
temp2->sreg1 = ins->inst_basereg;
temp2->sreg2 = temp->dreg;
temp2->dreg = mono_regstate_next_int (cfg->rs);
@@ -1995,7 +1995,7 @@
if (sum_reg == 0)
sum_reg = temp->dreg;
else {
- NEW_INS (cfg, temp2,
CEE_ADD);
+ NEW_INS (cfg, temp2,
OP_LADD);
temp2->dreg =
mono_regstate_next_int (cfg->rs);
temp2->sreg1 = sum_reg;
temp2->sreg2 =
temp->dreg;
@@ -2008,7 +2008,7 @@
}
break;
}
- case CEE_CONV_OVF_U4:
+ case OP_LCONV_TO_OVF_U4:
NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
temp->sreg1 = ins->sreg1;
temp->sreg2 = IA64_R0;
@@ -2018,7 +2018,7 @@
ins->opcode = OP_MOVE;
break;
- case CEE_CONV_OVF_I4_UN:
+ case OP_LCONV_TO_OVF_I4_UN:
NEW_INS (cfg, temp, OP_ICONST);
temp->inst_c0 = 0x7fffffff;
temp->dreg = mono_regstate_next_int (cfg->rs);
@@ -2185,7 +2185,6 @@
case OP_VOIDCALL_REG:
case OP_VOIDCALL_MEMBASE:
break;
- case CEE_CALL:
case OP_CALL:
case OP_CALL_REG:
case OP_CALL_MEMBASE:
@@ -2396,42 +2395,34 @@
ia64_mov_to_br (code, IA64_B6, ins->sreg1);
ia64_br_cond_reg (code, IA64_B6);
break;
- case CEE_ADD:
case OP_IADD:
case OP_LADD:
ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case CEE_SUB:
case OP_ISUB:
case OP_LSUB:
ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case CEE_AND:
case OP_IAND:
case OP_LAND:
ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case CEE_OR:
case OP_IOR:
case OP_LOR:
ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case CEE_XOR:
case OP_IXOR:
case OP_LXOR:
ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case CEE_NEG:
case OP_INEG:
case OP_LNEG:
ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
break;
- case CEE_NOT:
case OP_INOT:
case OP_LNOT:
ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
break;
- case CEE_SHL:
case OP_ISHL:
case OP_LSHL:
ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
@@ -2547,7 +2538,7 @@
case OP_LSHR_UN_IMM:
ia64_shr_u_imm (code, ins->dreg, ins->sreg1,
ins->inst_imm);
break;
- case CEE_MUL:
+ case OP_LMUL:
/* Based on gcc code */
ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
@@ -2832,48 +2823,38 @@
ia64_no_stop (code);
ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
break;
- case CEE_CONV_I1:
case OP_ICONV_TO_I1:
case OP_LCONV_TO_I1:
/* FIXME: Is this needed ? */
ia64_sxt1 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_I2:
case OP_ICONV_TO_I2:
case OP_LCONV_TO_I2:
/* FIXME: Is this needed ? */
ia64_sxt2 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_I4:
case OP_LCONV_TO_I4:
/* FIXME: Is this needed ? */
ia64_sxt4 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_U1:
case OP_ICONV_TO_U1:
case OP_LCONV_TO_U1:
/* FIXME: Is this needed */
ia64_zxt1 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_U2:
case OP_ICONV_TO_U2:
case OP_LCONV_TO_U2:
/* FIXME: Is this needed */
ia64_zxt2 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_U4:
case OP_LCONV_TO_U4:
/* FIXME: Is this needed */
ia64_zxt4 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_I8:
- case CEE_CONV_I:
case OP_ICONV_TO_I8:
case OP_ICONV_TO_I:
ia64_sxt4 (code, ins->dreg, ins->sreg1);
break;
- case CEE_CONV_U8:
- case CEE_CONV_U:
case OP_ICONV_TO_U8:
case OP_ICONV_TO_U:
ia64_zxt4 (code, ins->dreg, ins->sreg1);
@@ -2947,26 +2928,24 @@
ia64_ldfs (code, ins->dreg, ins->inst_basereg);
ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
break;
- case CEE_CONV_R4:
case OP_ICONV_TO_R4:
ia64_setf_sig (code, ins->dreg, ins->sreg1);
ia64_fcvt_xf (code, ins->dreg, ins->dreg);
ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
break;
- case CEE_CONV_R8:
case OP_ICONV_TO_R8:
ia64_setf_sig (code, ins->dreg, ins->sreg1);
ia64_fcvt_xf (code, ins->dreg, ins->dreg);
ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
break;
case OP_LCONV_TO_R8:
- /* FIXME: Difference with CEE_CONV_R8 ? */
+ /* FIXME: Difference with OP_ICONV_TO_R8 ? */
ia64_setf_sig (code, ins->dreg, ins->sreg1);
ia64_fcvt_xf (code, ins->dreg, ins->dreg);
ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
break;
case OP_LCONV_TO_R4:
- /* FIXME: Difference with CEE_CONV_R4 ? */
+ /* FIXME: Difference with OP_ICONV_TO_R4 ? */
ia64_setf_sig (code, ins->dreg, ins->sreg1);
ia64_fcvt_xf (code, ins->dreg, ins->dreg);
ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
@@ -3019,7 +2998,6 @@
case OP_VCALL:
case OP_VCALL2:
case OP_VOIDCALL:
- case CEE_CALL:
case OP_CALL:
call = (MonoCallInst*)ins;
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-sparc.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-sparc.c 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-sparc.c 2008-02-05
21:40:06 UTC (rev 94960)
@@ -1973,12 +1973,12 @@
}
}
break;
- case CEE_BEQ:
- case CEE_BNE_UN:
- case CEE_BLT:
- case CEE_BGT:
- case CEE_BGE:
- case CEE_BLE:
+ case OP_IBEQ:
+ case OP_IBNE_UN:
+ case OP_IBLT:
+ case OP_IBGT:
+ case OP_IBGE:
+ case OP_IBLE:
case OP_COND_EXC_EQ:
case OP_COND_EXC_GE:
case OP_COND_EXC_GT:
@@ -1999,22 +1999,22 @@
(last_ins->inst_imm == 0)) {
MonoInst *next = ins->next;
switch (ins->opcode) {
- case CEE_BEQ:
+ case OP_IBEQ:
ins->opcode = OP_SPARC_BRZ;
break;
- case CEE_BNE_UN:
+ case OP_IBNE_UN:
ins->opcode = OP_SPARC_BRNZ;
break;
- case CEE_BLT:
+ case OP_IBLT:
ins->opcode = OP_SPARC_BRLZ;
break;
- case CEE_BGT:
+ case OP_IBGT:
ins->opcode = OP_SPARC_BRGZ;
break;
- case CEE_BGE:
+ case OP_IBGE:
ins->opcode = OP_SPARC_BRGEZ;
break;
- case CEE_BLE:
+ case OP_IBLE:
ins->opcode = OP_SPARC_BRLEZ;
break;
case OP_COND_EXC_EQ:
@@ -2045,8 +2045,6 @@
continue;
}
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
/*
* OP_MOVE reg, reg
@@ -2287,7 +2285,6 @@
case OP_VOIDCALL_REG:
case OP_VOIDCALL_MEMBASE:
break;
- case CEE_CALL:
case OP_CALL:
case OP_CALL_REG:
case OP_CALL_MEMBASE:
@@ -2836,26 +2833,22 @@
EMIT_LOAD_MEMBASE (ins, ldx);
break;
#endif
- case CEE_CONV_I1:
case OP_ICONV_TO_I1:
sparc_sll_imm (code, ins->sreg1, 24, sparc_o7);
sparc_sra_imm (code, sparc_o7, 24, ins->dreg);
break;
- case CEE_CONV_I2:
case OP_ICONV_TO_I2:
sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
sparc_sra_imm (code, sparc_o7, 16, ins->dreg);
break;
- case CEE_CONV_U1:
case OP_ICONV_TO_U1:
sparc_and_imm (code, FALSE, ins->sreg1, 0xff,
ins->dreg);
break;
- case CEE_CONV_U2:
case OP_ICONV_TO_U2:
sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
sparc_srl_imm (code, sparc_o7, 16, ins->dreg);
break;
- case CEE_CONV_OVF_U4:
+ case OP_LCONV_TO_OVF_U4:
/* Only used on V9 */
sparc_cmp_imm (code, ins->sreg1, 0);
mono_add_patch_info (cfg, (guint8*)(code) -
(cfg)->native_code,
@@ -2871,20 +2864,10 @@
sparc_nop (code);
sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
break;
- case CEE_CONV_OVF_I4_UN:
+ case OP_LCONV_TO_OVF_I4_UN:
/* Only used on V9 */
NOT_IMPLEMENTED;
break;
- case CEE_CONV_U:
- case CEE_CONV_U8:
- /* Only used on V9 */
- sparc_srl_imm (code, ins->sreg1, 0, ins->dreg);
- break;
- case CEE_CONV_I:
- case CEE_CONV_I8:
- /* Only used on V9 */
- sparc_sra_imm (code, ins->sreg1, 0, ins->dreg);
- break;
case OP_COMPARE:
case OP_LCOMPARE:
case OP_ICOMPARE:
@@ -2913,7 +2896,6 @@
case OP_IADDCC:
sparc_add (code, TRUE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
- case CEE_ADD:
case OP_IADD:
sparc_add (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
@@ -2936,7 +2918,6 @@
case OP_ISUBCC:
sparc_sub (code, TRUE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
- case CEE_SUB:
case OP_ISUB:
sparc_sub (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
@@ -2955,7 +2936,6 @@
case OP_ISBB_IMM:
EMIT_ALU_IMM (ins, subx, TRUE);
break;
- case CEE_AND:
case OP_IAND:
sparc_and (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
@@ -2963,7 +2943,6 @@
case OP_IAND_IMM:
EMIT_ALU_IMM (ins, and, FALSE);
break;
- case CEE_DIV:
case OP_IDIV:
/* Sign extend sreg1 into %y */
sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
@@ -2971,7 +2950,6 @@
sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2,
ins->dreg);
EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code,
sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
break;
- case CEE_DIV_UN:
case OP_IDIV_UN:
sparc_wry (code, sparc_g0, sparc_g0);
sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
@@ -3010,7 +2988,6 @@
}
break;
}
- case CEE_REM:
case OP_IREM:
/* Sign extend sreg1 into %y */
sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
@@ -3020,7 +2997,6 @@
sparc_smul (code, FALSE, ins->sreg2, sparc_o7,
sparc_o7);
sparc_sub (code, FALSE, ins->sreg1, sparc_o7,
ins->dreg);
break;
- case CEE_REM_UN:
case OP_IREM_UN:
sparc_wry (code, sparc_g0, sparc_g0);
sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2,
sparc_o7);
@@ -3045,7 +3021,6 @@
}
sparc_sub (code, FALSE, ins->sreg1, sparc_o7,
ins->dreg);
break;
- case CEE_OR:
case OP_IOR:
sparc_or (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
@@ -3053,7 +3028,6 @@
case OP_IOR_IMM:
EMIT_ALU_IMM (ins, or, FALSE);
break;
- case CEE_XOR:
case OP_IXOR:
sparc_xor (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
@@ -3061,7 +3035,6 @@
case OP_IXOR_IMM:
EMIT_ALU_IMM (ins, xor, FALSE);
break;
- case CEE_SHL:
case OP_ISHL:
sparc_sll (code, ins->sreg1, ins->sreg2, ins->dreg);
break;
@@ -3074,7 +3047,6 @@
sparc_sll (code, ins->sreg1, sparc_o7,
ins->dreg);
}
break;
- case CEE_SHR:
case OP_ISHR:
sparc_sra (code, ins->sreg1, ins->sreg2, ins->dreg);
break;
@@ -3096,7 +3068,6 @@
sparc_srl (code, ins->sreg1, sparc_o7,
ins->dreg);
}
break;
- case CEE_SHR_UN:
case OP_ISHR_UN:
sparc_srl (code, ins->sreg1, ins->sreg2, ins->dreg);
break;
@@ -3133,17 +3104,14 @@
sparc_srlx (code, ins->sreg1, sparc_o7,
ins->dreg);
}
break;
- case CEE_NOT:
case OP_INOT:
/* can't use sparc_not */
sparc_xnor (code, FALSE, ins->sreg1, sparc_g0,
ins->dreg);
break;
- case CEE_NEG:
case OP_INEG:
/* can't use sparc_neg */
sparc_sub (code, FALSE, sparc_g0, ins->sreg1,
ins->dreg);
break;
- case CEE_MUL:
case OP_IMUL:
sparc_smul (code, FALSE, ins->sreg1, ins->sreg2,
ins->dreg);
break;
@@ -3166,7 +3134,6 @@
EMIT_ALU_IMM (ins, smul, FALSE);
break;
}
- case CEE_MUL_OVF:
case OP_IMUL_OVF:
sparc_smul (code, TRUE, ins->sreg1, ins->sreg2,
ins->dreg);
sparc_rdy (code, sparc_g1);
@@ -3174,7 +3141,6 @@
sparc_cmp (code, sparc_g1, sparc_o7);
EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne,
"OverflowException", TRUE, sparc_icc_short);
break;
- case CEE_MUL_OVF_UN:
case OP_IMUL_OVF_UN:
sparc_umul (code, TRUE, ins->sreg1, ins->sreg2,
ins->dreg);
sparc_rdy (code, sparc_o7);
@@ -3195,8 +3161,6 @@
mono_add_patch_info (cfg, offset,
(MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
sparc_set_template (code, ins->dreg);
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
if (ins->sreg1 != ins->dreg)
sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
@@ -3235,7 +3199,6 @@
case OP_VCALL:
case OP_VCALL2:
case OP_VOIDCALL:
- case CEE_CALL:
case OP_CALL:
call = (MonoCallInst*)ins;
g_assert (!call->virtual);
@@ -3618,22 +3581,6 @@
case OP_SPARC_COND_EXC_NEZ:
EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brnz,
ins->inst_p1);
break;
- case CEE_BEQ:
- case CEE_BNE_UN:
- case CEE_BLT:
- case CEE_BLT_UN:
- case CEE_BGT:
- case CEE_BGT_UN:
- case CEE_BGE:
- case CEE_BGE_UN:
- case CEE_BLE:
- case CEE_BLE_UN: {
- if (sparcv9)
- EMIT_COND_BRANCH_PREDICTED (ins,
opcode_to_sparc_cond (ins->opcode), 1, 1);
- else
- EMIT_COND_BRANCH (ins, opcode_to_sparc_cond
(ins->opcode), 1, 1);
- break;
- }
case OP_IBEQ:
case OP_IBNE_UN:
@@ -3749,7 +3696,6 @@
sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
#endif
break;
- case CEE_CONV_R4:
case OP_ICONV_TO_R4: {
gint32 offset = cfg->arch.float_spill_slot_offset;
#ifdef SPARCV9
@@ -3776,7 +3722,6 @@
sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
break;
}
- case CEE_CONV_R8:
case OP_ICONV_TO_R8: {
gint32 offset = cfg->arch.float_spill_slot_offset;
#ifdef SPARCV9
@@ -3852,10 +3797,6 @@
sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
#endif
break;
- case CEE_CONV_R_UN:
- /* Emulated */
- g_assert_not_reached ();
- break;
case OP_LCONV_TO_R_UN: {
/* Emulated */
g_assert_not_reached ();
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-x86.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-x86.c 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-x86.c 2008-02-05
21:40:06 UTC (rev 94960)
@@ -1750,7 +1750,7 @@
(last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? CEE_CONV_I1 : CEE_CONV_U1;
+ ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
ins->sreg1 = last_ins->sreg1;
}
break;
@@ -1766,12 +1766,10 @@
if (last_ins && (last_ins->opcode ==
OP_STOREI2_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? CEE_CONV_I2 : CEE_CONV_U2;
+ ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
ins->sreg1 = last_ins->sreg1;
}
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
/*
* Removes:
@@ -1971,7 +1969,7 @@
(last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? CEE_CONV_I1 : CEE_CONV_U1;
+ ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
ins->sreg1 = last_ins->sreg1;
}
break;
@@ -1987,12 +1985,10 @@
if (last_ins && (last_ins->opcode ==
OP_STOREI2_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? CEE_CONV_I2 : CEE_CONV_U2;
+ ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
ins->sreg1 = last_ins->sreg1;
}
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
/*
* Removes:
@@ -2278,7 +2274,6 @@
/* Move return value to the target register */
switch (ins->opcode) {
- case CEE_CALL:
case OP_CALL:
case OP_CALL_REG:
case OP_CALL_MEMBASE:
@@ -2552,21 +2547,17 @@
case OP_LOADI2_MEMBASE:
x86_widen_membase (code, ins->dreg, ins->inst_basereg,
ins->inst_offset, TRUE, TRUE);
break;
- case CEE_CONV_I1:
case OP_ICONV_TO_I1:
case OP_SEXT_I1:
x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE,
FALSE);
break;
- case CEE_CONV_I2:
case OP_ICONV_TO_I2:
case OP_SEXT_I2:
x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
break;
- case CEE_CONV_U1:
case OP_ICONV_TO_U1:
x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE,
FALSE);
break;
- case CEE_CONV_U2:
case OP_ICONV_TO_U2:
x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE,
TRUE);
break;
@@ -2670,7 +2661,6 @@
break;
case OP_ADDCC:
case OP_IADDCC:
- case CEE_ADD:
case OP_IADD:
x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
break;
@@ -2689,7 +2679,6 @@
break;
case OP_SUBCC:
case OP_ISUBCC:
- case CEE_SUB:
case OP_ISUB:
x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
break;
@@ -2706,7 +2695,6 @@
case OP_ISBB_IMM:
x86_alu_reg_imm (code, X86_SBB, ins->dreg,
ins->inst_imm);
break;
- case CEE_AND:
case OP_IAND:
x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
break;
@@ -2714,9 +2702,7 @@
case OP_IAND_IMM:
x86_alu_reg_imm (code, X86_AND, ins->sreg1,
ins->inst_imm);
break;
- case CEE_DIV:
case OP_IDIV:
- case CEE_REM:
case OP_IREM:
/*
* The code is the same for div/rem, the allocator will
allocate dreg
@@ -2733,9 +2719,7 @@
x86_div_reg (code, ins->sreg2, TRUE);
}
break;
- case CEE_DIV_UN:
case OP_IDIV_UN:
- case CEE_REM_UN:
case OP_IREM_UN:
if (ins->sreg2 == X86_EDX) {
x86_push_reg (code, ins->sreg2);
@@ -2783,7 +2767,6 @@
}
break;
}
- case CEE_OR:
case OP_IOR:
x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
break;
@@ -2791,7 +2774,6 @@
case OP_IOR_IMM:
x86_alu_reg_imm (code, X86_OR, ins->sreg1,
ins->inst_imm);
break;
- case CEE_XOR:
case OP_IXOR:
x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
break;
@@ -2799,12 +2781,10 @@
case OP_IXOR_IMM:
x86_alu_reg_imm (code, X86_XOR, ins->sreg1,
ins->inst_imm);
break;
- case CEE_SHL:
case OP_ISHL:
g_assert (ins->sreg2 == X86_ECX);
x86_shift_reg (code, X86_SHL, ins->dreg);
break;
- case CEE_SHR:
case OP_ISHR:
g_assert (ins->sreg2 == X86_ECX);
x86_shift_reg (code, X86_SAR, ins->dreg);
@@ -2817,7 +2797,6 @@
case OP_ISHR_UN_IMM:
x86_shift_reg_imm (code, X86_SHR, ins->dreg,
ins->inst_imm);
break;
- case CEE_SHR_UN:
case OP_ISHR_UN:
g_assert (ins->sreg2 == X86_ECX);
x86_shift_reg (code, X86_SHR, ins->dreg);
@@ -2907,16 +2886,13 @@
x86_shift_reg_imm (code, X86_SHR,
ins->backend.reg3, ins->inst_imm);
}
break;
- case CEE_NOT:
case OP_INOT:
x86_not_reg (code, ins->sreg1);
break;
- case CEE_NEG:
case OP_INEG:
x86_neg_reg (code, ins->sreg1);
break;
- case CEE_MUL:
case OP_IMUL:
x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
break;
@@ -2979,12 +2955,10 @@
break;
}
break;
- case CEE_MUL_OVF:
case OP_IMUL_OVF:
x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE,
"OverflowException");
break;
- case CEE_MUL_OVF_UN:
case OP_IMUL_OVF_UN: {
/* the mul operation and the exception check should
most likely be split */
int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
@@ -3053,12 +3027,9 @@
mono_add_patch_info (cfg, offset,
(MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
break;
- case CEE_CONV_I4:
case OP_MOVE:
x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
break;
- case CEE_CONV_U4:
- g_assert_not_reached ();
case OP_JMP: {
/*
* Note: this 'frame destruction' logic is useful for
tail calls, too.
@@ -3119,7 +3090,6 @@
case OP_VCALL:
case OP_VCALL2:
case OP_VOIDCALL:
- case CEE_CALL:
case OP_CALL:
call = (MonoCallInst*)ins;
if (ins->flags & MONO_INST_HAS_METHOD)
@@ -3366,16 +3336,6 @@
case OP_COND_EXC_INC:
EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table
[ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN),
ins->inst_p1);
break;
- case CEE_BEQ:
- case CEE_BNE_UN:
- case CEE_BLT:
- case CEE_BLT_UN:
- case CEE_BGT:
- case CEE_BGT_UN:
- case CEE_BGE:
- case CEE_BGE_UN:
- case CEE_BLE:
- case CEE_BLE_UN:
case OP_IBEQ:
case OP_IBNE_UN:
case OP_IBLT:
@@ -3463,8 +3423,6 @@
case OP_LOADR4_MEMBASE:
x86_fld_membase (code, ins->inst_basereg,
ins->inst_offset, FALSE);
break;
- case CEE_CONV_R4: /* FIXME: change precision */
- case CEE_CONV_R8:
case OP_ICONV_TO_R4:
case OP_ICONV_TO_R8:
x86_push_reg (code, ins->sreg1);
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini.c 2008-02-05
21:39:19 UTC (rev 94959)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini.c 2008-02-05
21:40:06 UTC (rev 94960)
@@ -11686,24 +11686,22 @@
remap_table = g_new0 (gint16, OP_LAST);
#if SIZEOF_VOID_P == 8
- remap_table [CEE_CONV_I1] = OP_LCONV_TO_I1;
- remap_table [CEE_CONV_I2] = OP_LCONV_TO_I2;
- remap_table [CEE_CONV_U1] = OP_LCONV_TO_U1;
- remap_table [CEE_CONV_U2] = OP_LCONV_TO_U2;
remap_table [CEE_CONV_U8] = OP_ZEXT_I4;
remap_table [CEE_CONV_U] = OP_ZEXT_I4;
remap_table [CEE_CONV_I8] = OP_SEXT_I4;
remap_table [CEE_CONV_I] = OP_SEXT_I4;
- remap_table [CEE_CONV_R4] = OP_ICONV_TO_R4;
- remap_table [CEE_CONV_R8] = OP_ICONV_TO_R8;
- remap_table [CEE_CONV_I4] = OP_MOVE;
- remap_table [CEE_CONV_U4] = OP_MOVE;
remap_table [CEE_CONV_OVF_U4] = OP_LCONV_TO_OVF_U4;
remap_table [CEE_CONV_OVF_I4_UN] = OP_LCONV_TO_OVF_I4_UN;
#else
- g_assert_not_reached ();
#endif
-
+ remap_table [CEE_CONV_R4] = OP_ICONV_TO_R4;
+ remap_table [CEE_CONV_R8] = OP_ICONV_TO_R8;
+ remap_table [CEE_CONV_I4] = OP_MOVE;
+ remap_table [CEE_CONV_U4] = OP_MOVE;
+ remap_table [CEE_CONV_I1] = REMAP_OPCODE (CONV_TO_I1);
+ remap_table [CEE_CONV_I2] = REMAP_OPCODE (CONV_TO_I2);
+ remap_table [CEE_CONV_U1] = REMAP_OPCODE (CONV_TO_U1);
+ remap_table [CEE_CONV_U2] = REMAP_OPCODE (CONV_TO_U2);
remap_table [CEE_ADD] = REMAP_OPCODE (ADD);
remap_table [CEE_SUB] = REMAP_OPCODE (SUB);
remap_table [CEE_MUL] = REMAP_OPCODE (MUL);
@@ -11730,15 +11728,15 @@
remap_table [CEE_BGE_UN] = REMAP_OPCODE (BGE_UN);
remap_table [CEE_BLE] = REMAP_OPCODE (BLE);
remap_table [CEE_BLE_UN] = REMAP_OPCODE (BLE_UN);
+ remap_table [CEE_MUL_OVF] = REMAP_OPCODE (MUL_OVF);
+ remap_table [CEE_MUL_OVF_UN] = REMAP_OPCODE (MUL_OVF_UN);
}
-#ifdef MONO_ARCH_ENABLE_NORMALIZE_OPCODES
MONO_BB_FOR_EACH_INS (bb, ins) {
int remapped = remap_table [ins->opcode];
if (remapped)
ins->opcode = remapped;
}
-#endif
}
void
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