Author: zoltan
Date: 2008-02-15 06:52:35 -0500 (Fri, 15 Feb 2008)
New Revision: 95734
Modified:
branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog
branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md
branches/vargaz/mini-linear-il/mono/mono/mini/method-to-ir.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini-ops.h
Log:
2008-02-15 Zoltan Varga <[EMAIL PROTECTED]>
* method-to-ir.c (mini_emit_inst_for_method): Fix 64 bit issues in
array access
implementation.
(mini_emit_ldelema_1_ins): Ditto.
* mini-ia64.c cpu-ia64.md: Fix ia64 build.
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog 2008-02-15
11:50:15 UTC (rev 95733)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog 2008-02-15
11:52:35 UTC (rev 95734)
@@ -1,3 +1,11 @@
+2008-02-15 Zoltan Varga <[EMAIL PROTECTED]>
+
+ * method-to-ir.c (mini_emit_inst_for_method): Fix 64 bit issues in
array access
+ implementation.
+ (mini_emit_ldelema_1_ins): Ditto.
+
+ * mini-ia64.c cpu-ia64.md: Fix ia64 build.
+
2008-02-14 Zoltan Varga <[EMAIL PROTECTED]>
* cpu-sparc.md mini-sparc.c: Fix sparc build.
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md 2008-02-15
11:50:15 UTC (rev 95733)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/cpu-ia64.md 2008-02-15
11:52:35 UTC (rev 95734)
@@ -8,65 +8,23 @@
break: len:48
jmp: len:48
br: len:48
-<<<<<<< .working
-jump_table: dest:i len:48
-
-nop: len:0
-dummy_use: len:0
-dummy_store: len:0
-not_reached: len:0
-not_null: src1:i len:0
-
-long_add: dest:i src1:i src2:i len:48
-long_sub: dest:i src1:i src2:i len:48
-long_and: dest:i src1:i src2:i len:48
-long_or: dest:i src1:i src2:i len:48
-long_xor: dest:i src1:i src2:i len:48
-long_shl: dest:i src1:i src2:s len:48
-long_shr: dest:i src1:i src2:s len:48
-long_shr_un: dest:i src1:i src2:s len:48
-
-long_neg: dest:i src1:i len:48
-long_not: dest:i src1:i len:48
-long_conv_to_i1: dest:i src1:i len:48
-long_conv_to_u1: dest:i src1:i len:48
-long_conv_to_i2: dest:i src1:i len:48
-long_conv_to_u2: dest:i src1:i len:48
-long_conv_to_i4: dest:i src1:i len:48
-long_conv_to_u4: dest:i src1:i len:48
-long_conv_to_i8: dest:i src1:i len:48
-long_conv_to_u8: dest:i src1:i len:112
-long_conv_to_r4: dest:f src1:i len:112
-long_conv_to_r8: dest:f src1:i len:112
-long_conv_to_r_un: dest:f src1:i len:48
-long_conv_to_ovf_i4_un: dest:i src1:i len:96
-long_conv_to_ovf_u4: dest:i src1:i len:48
-
-=======
->>>>>>> .merge-right.r95529
throw: src1:i len:96
rethrow: src1:i len:48
ckfinite: dest:f src1:f len:48
-<<<<<<< .working
-
-=======
mul.ovf: dest:i src1:i src2:i len:48
# this opcode is handled specially in the code generator
mul.ovf.un: dest:i src1:i src2:i len:48
conv.u: dest:i src1:i len:48
->>>>>>> .merge-right.r95529
ceq: dest:c len:48
cgt: dest:c len:48
cgt.un: dest:c len:48
clt: dest:c len:48
clt.un: dest:c len:48
localloc: dest:i src1:i len:92
-localloc_imm: dest:i len:92
compare: src1:i src2:i len:48
lcompare: src1:i src2:i len:48
icompare: src1:i src2:i len:48
compare_imm: src1:i len:48
-lcompare_imm: src1:i len:48
icompare_imm: src1:i len:48
fcompare: src1:f src2:f clob:a len:48
oparglist: src1:b len:48
@@ -75,10 +33,7 @@
setret: dest:r src1:i len:48
setlret: dest:r src1:i src2:i len:48
checkthis: src1:b len:48
-
call: dest:r clob:c len:80
-call_reg: dest:r src1:i len:80 clob:c
-call_membase: dest:r src1:b len:80 clob:c
voidcall: clob:c len:80
voidcall_reg: src1:i clob:c len:80
voidcall_membase: src1:b clob:c len:80
@@ -91,10 +46,8 @@
vcall: len:80 clob:c
vcall_reg: src1:i len:80 clob:c
vcall_membase: src1:b len:80 clob:c
-vcall2: len:80 clob:c
-vcall2_reg: src1:i len:80 clob:c
-vcall2_membase: src1:b len:80 clob:c
-
+call_reg: dest:r src1:i len:80 clob:c
+call_membase: dest:r src1:b len:80 clob:c
iconst: dest:i len:48
i8const: dest:i len:48
r4const: dest:f len:48
@@ -156,21 +109,6 @@
cond_exc_nc: len:48
cond_exc_iov: len:48
cond_exc_ic: len:48
-<<<<<<< .working
-
-long_mul: dest:i src1:i src2:i len:48
-long_mul_imm: dest:i src1:i src2:i len:48
-long_div: dest:a src1:a src2:i len:48 clob:d
-long_div_un: dest:a src1:a src2:i len:48 clob:d
-long_rem: dest:d src1:a src2:i len:48 clob:a
-long_rem_un: dest:d src1:a src2:i len:48 clob:a
-long_conv_to_ovf_i: dest:i src1:i src2:i len:48
-long_mul_ovf: dest:i src1:i src2:i len:48
-long_mul_ovf_un: dest:i src1:i src2:i len:48
-long_conv_to_r_un: dest:f src1:i src2:i len:48
-
-=======
->>>>>>> .merge-right.r95529
float_beq: len:48
float_bne_un: len:48
float_blt: len:48
@@ -195,6 +133,7 @@
float_conv_to_i4: dest:i src1:f len:112
float_conv_to_i8: dest:i src1:f len:112
float_conv_to_r4: dest:f src1:f len:112
+float_conv_to_r8: dest:f src1:f len:112
float_conv_to_u4: dest:i src1:f len:112
float_conv_to_u8: dest:i src1:f len:112
float_conv_to_u2: dest:i src1:f len:112
@@ -215,12 +154,10 @@
float_clt_un_membase: dest:i src1:f src2:b len:48
float_conv_to_u: dest:i src1:f len:48
fmove: dest:f src1:f len:48
-
call_handler: len:96
start_handler: len:96
endfilter: len:96
endfinally: len:96
-
aot_const: dest:i len:48
tls_get: dest:i len:48
atomic_add_i4: src1:b src2:i dest:i len:48
@@ -309,28 +246,6 @@
int_conv_to_r4: dest:f src1:i len:112
int_conv_to_r8: dest:f src1:i len:112
-<<<<<<< .working
-int_conv_to_i1: dest:i src1:i len:48
-int_conv_to_u1: dest:i src1:i len:48
-int_conv_to_i2: dest:i src1:i len:48
-int_conv_to_u2: dest:i src1:i len:48
-int_conv_to_i4: dest:i src1:i len:48
-int_conv_to_u4: dest:i src1:i len:48
-int_conv_to_i8: dest:i src1:i len:48
-int_conv_to_u8: dest:i src1:i len:48
-int_conv_to_r4: dest:f src1:i len:48
-int_conv_to_r8: dest:f src1:i len:48
-
-long_add_imm: dest:i src1:i len:48
-long_sub_imm: dest:i src1:i len:48
-long_and_imm: dest:i src1:i len:48
-long_or_imm: dest:i src1:i len:48
-long_xor_imm: dest:i src1:i len:48
-long_shl_imm: dest:i src1:i len:48
-long_shr_imm: dest:i src1:i len:48
-long_shr_un_imm: dest:i src1:i len:48
-
-=======
# 64 bit opcodes
long_add: dest:i src1:i src2:i len:48
long_sub: dest:i src1:i src2:i len:48
@@ -381,7 +296,6 @@
long_ble_un: len:48
long_blt_un: len:48
->>>>>>> .merge-right.r95529
ia64_cmp4_eq: src1:i src2:i len:48
ia64_cmp4_ne: src1:i src2:i len:48
ia64_cmp4_le: src1:i src2:i len:48
@@ -457,18 +371,33 @@
ia64_loadr4_membase_inc: dest:b src1:i len:48
ia64_loadr8_membase_inc: dest:b src1:i len:48
-long_ceq: dest:c len:64
-long_cgt: dest:c len:64
-long_cgt_un: dest:c len:64
-long_clt: dest:c len:64
-long_clt_un: dest:c len:64
-long_beq: len:64
-long_bne_un: len:64
-long_blt: len:64
-long_blt_un: len:64
-long_bgt: len:64
-long_bgt_un: len:64
-long_bge: len:64
-long_bge_un: len:64
-long_ble: len:64
-long_ble_un: len:64
+# Linear IR opcodes
+nop: len:0
+dummy_use: len:0
+dummy_store: len:0
+not_reached: len:0
+not_null: src1:i len:0
+
+jump_table: dest:i len:48
+
+localloc_imm: dest:i len:92
+
+vcall2: len:80 clob:c
+vcall2_reg: src1:i len:80 clob:c
+vcall2_membase: src1:b len:80 clob:c
+
+int_conv_to_i1: dest:i src1:i len:48
+int_conv_to_u1: dest:i src1:i len:48
+int_conv_to_i2: dest:i src1:i len:48
+int_conv_to_u2: dest:i src1:i len:48
+int_conv_to_i4: dest:i src1:i len:48
+int_conv_to_u4: dest:i src1:i len:48
+int_conv_to_i8: dest:i src1:i len:48
+int_conv_to_u8: dest:i src1:i len:48
+
+long_add_imm: dest:i src1:i len:48
+long_sub_imm: dest:i src1:i len:48
+long_and_imm: dest:i src1:i len:48
+long_or_imm: dest:i src1:i len:48
+long_xor_imm: dest:i src1:i len:48
+
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/method-to-ir.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/method-to-ir.c
2008-02-15 11:50:15 UTC (rev 95733)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/method-to-ir.c
2008-02-15 11:52:35 UTC (rev 95734)
@@ -3010,7 +3010,7 @@
guint32 imt_slot = mono_method_get_imt_slot (method);
emit_imt_argument (cfg, call);
slot_reg = vtable_reg;
- call->inst.inst_offset = (imt_slot - MONO_IMT_SIZE) *
SIZEOF_VOID_P;
+ call->inst.inst_offset = ((gint32)imt_slot -
MONO_IMT_SIZE) * SIZEOF_VOID_P;
#else
slot_reg = alloc_preg (cfg);
mini_emit_load_intf_reg_vtable (cfg, slot_reg,
vtable_reg, method->klass);
@@ -3747,7 +3747,7 @@
{
MonoInst *ins;
guint32 size;
- int mult_reg, add_reg, array_reg, index_reg;
+ int mult_reg, add_reg, array_reg, index_reg, index2_reg;
mono_class_init (klass);
size = mono_class_array_element_size (klass);
@@ -3757,8 +3757,16 @@
array_reg = arr->dreg;
index_reg = index->dreg;
- MONO_EMIT_BOUNDS_CHECK (cfg, array_reg, MonoArray, max_length,
index_reg);
+#if SIZEOF_VOID_P == 8
+ /* The array reg is 64 bits but the index reg is only 32 */
+ index2_reg = alloc_preg (cfg);
+ MONO_EMIT_NEW_UNALU (cfg, OP_SEXT_I4, index2_reg, index_reg);
+#else
+ index2_reg = index_reg;
+#endif
+ MONO_EMIT_BOUNDS_CHECK (cfg, array_reg, MonoArray, max_length,
index2_reg);
+
#ifdef __i386__
if (size == 1 || size == 2 || size == 4 || size == 8) {
static const int fast_log2 [] = { 1, 0, 1, -1, 2, -1, -1, -1, 3
};
@@ -3778,12 +3786,7 @@
#ifdef __x86_64__
if (size == 1 || size == 2 || size == 4 || size == 8) {
static const int fast_log2 [] = { 1, 0, 1, -1, 2, -1, -1, -1, 3
};
- int index2_reg;
- /* The array reg is 64 bits but the index reg is only 32 */
- index2_reg = alloc_preg (cfg);
- MONO_EMIT_NEW_UNALU (cfg, OP_SEXT_I4, index2_reg, index_reg);
-
MONO_INST_NEW (cfg, ins, OP_X86_LEA);
ins->dreg = add_reg;
ins->sreg1 = array_reg;
@@ -3797,7 +3800,7 @@
}
#endif
- MONO_EMIT_NEW_BIALU_IMM (cfg, OP_MUL_IMM, mult_reg, index_reg, size);
+ MONO_EMIT_NEW_BIALU_IMM (cfg, OP_MUL_IMM, mult_reg, index2_reg, size);
MONO_EMIT_NEW_BIALU (cfg, OP_PADD, add_reg, array_reg, mult_reg);
NEW_BIALU_IMM (cfg, ins, OP_PADD_IMM, add_reg, add_reg, G_STRUCT_OFFSET
(MonoArray, vector));
ins->type = STACK_PTR;
@@ -3921,11 +3924,18 @@
if (cmethod->klass == mono_defaults.string_class) {
if (strcmp (cmethod->name, "get_Chars") == 0) {
int dreg = alloc_ireg (cfg);
+ int index_reg = alloc_preg (cfg);
int mult_reg = alloc_preg (cfg);
int add_reg = alloc_preg (cfg);
-
- MONO_EMIT_BOUNDS_CHECK (cfg, args [0]->dreg,
MonoString, length, args [1]->dreg);
- MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, mult_reg,
args [1]->dreg, 1);
+
+#if SIZEOF_VOID_P == 8
+ /* The array reg is 64 bits but the index reg is only
32 */
+ MONO_EMIT_NEW_UNALU (cfg, OP_SEXT_I4, index_reg, args
[1]->dreg);
+#else
+ index_reg = args [1]->dreg;
+#endif
+ MONO_EMIT_BOUNDS_CHECK (cfg, args [0]->dreg,
MonoString, length, index_reg);
+ MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, mult_reg,
index_reg, 1);
MONO_EMIT_NEW_BIALU (cfg, OP_PADD, add_reg, mult_reg,
args [0]->dreg);
EMIT_NEW_LOAD_MEMBASE (cfg, ins, OP_LOADU2_MEMBASE,
dreg,
add_reg,
G_STRUCT_OFFSET (MonoString, chars));
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c 2008-02-15
11:50:15 UTC (rev 95733)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-ia64.c 2008-02-15
11:52:35 UTC (rev 95734)
@@ -1036,6 +1036,12 @@
mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
break;
+ case ArgInFloatRegR4:
+ arg->opcode = OP_FCONV_TO_R4;
+ arg->dreg = mono_alloc_freg (cfg);
+
+ mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
+ break;
default:
g_assert_not_reached ();
}
@@ -1123,8 +1129,8 @@
} else {
MonoType *arg_type;
- in = call->args [i];
MONO_INST_NEW (cfg, arg, OP_OUTARG);
+ in = call->args [i];
arg->cil_code = in->cil_code;
arg->inst_left = in;
arg->type = in->type;
@@ -1165,15 +1171,6 @@
vtaddr = mono_compile_create_var (cfg,
&mono_defaults.int_class->byval_arg, OP_LOCAL);
- /* Trees can't be shared so make a copy
*/
- MONO_INST_NEW (cfg, arg, CEE_STIND_I);
- arg->cil_code = in->cil_code;
- arg->ssa_op = MONO_SSA_STORE;
- arg->inst_left = vtaddr;
- arg->inst_right = in;
- arg->type = in->type;
- MONO_INST_LIST_ADD_TAIL (&arg->node,
&call->out_args);
-
/*
* Part of the structure is passed in
registers.
*/
@@ -1211,7 +1208,10 @@
MONO_INST_NEW (cfg, load,
load_op);
load->inst_left = load2;
- MONO_INST_NEW (cfg, set_reg,
OP_OUTARG_REG);
+ if (j == 0)
+ set_reg = arg;
+ else
+ MONO_INST_NEW (cfg,
set_reg, OP_OUTARG_REG);
add_outarg_reg (cfg, call,
set_reg, arg_storage, dest_reg, load);
if (set_reg != call->out_args) {
set_reg->next =
call->out_args;
@@ -1239,7 +1239,10 @@
MONO_INST_NEW (cfg, load,
CEE_LDIND_I);
load->inst_left = load2;
- MONO_INST_NEW (cfg, outarg,
OP_OUTARG);
+ if (j == 0)
+ outarg = arg;
+ else
+ MONO_INST_NEW (cfg,
outarg, OP_OUTARG);
outarg->inst_left = load;
outarg->inst_imm = 16 +
ainfo->offset + (slot - 8) * 8;
@@ -1269,7 +1272,6 @@
arg->opcode = OP_OUTARG_VT;
arg->inst_right = stack_addr;
- MONO_INST_LIST_ADD_TAIL (&arg->node,
&call->out_args);
}
}
else {
@@ -1278,7 +1280,6 @@
add_outarg_reg (cfg, call, arg,
ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
break;
case ArgInFloatReg:
- case ArgInFloatRegR4:
add_outarg_reg (cfg, call, arg,
ainfo->storage, ainfo->reg, in);
break;
case ArgOnStack:
@@ -1292,7 +1293,6 @@
default:
g_assert_not_reached ();
}
- MONO_INST_LIST_ADD_TAIL (&arg->node,
&call->out_args);
}
}
}
@@ -1439,6 +1439,7 @@
add_outarg_reg2 (cfg, call, ainfo->storage,
cfg->arch.reg_out0 + ainfo->reg, in);
break;
case ArgInFloatReg:
+ case ArgInFloatRegR4:
add_outarg_reg2 (cfg, call, ainfo->storage,
ainfo->reg, in);
break;
case ArgOnStack:
@@ -1686,11 +1687,8 @@
NEW_INS (cfg, temp, OP_I8CONST);
temp->inst_c0 = ins->inst_offset;
temp->dreg = mono_regstate_next_int (cfg->rs);
-<<<<<<< .working
+
NEW_INS (cfg, temp2, OP_LADD);
-=======
- NEW_INS (cfg, ins, temp2, OP_LADD);
->>>>>>> .merge-right.r95529
temp2->sreg1 = ins->inst_destbasereg;
temp2->sreg2 = temp->dreg;
temp2->dreg = mono_regstate_next_int (cfg->rs);
@@ -1748,11 +1746,7 @@
NEW_INS (cfg, temp, OP_I8CONST);
temp->inst_c0 = ins->inst_offset;
temp->dreg = mono_regstate_next_int (cfg->rs);
-<<<<<<< .working
NEW_INS (cfg, temp2, OP_LADD);
-=======
- NEW_INS (cfg, ins, temp2, OP_LADD);
->>>>>>> .merge-right.r95529
temp2->sreg1 = ins->inst_destbasereg;
temp2->sreg2 = temp->dreg;
temp2->dreg = mono_regstate_next_int (cfg->rs);
@@ -1791,11 +1785,7 @@
NEW_INS (cfg, temp, OP_I8CONST);
temp->inst_c0 = ins->inst_offset;
temp->dreg = mono_regstate_next_int (cfg->rs);
-<<<<<<< .working
NEW_INS (cfg, temp2, OP_LADD);
-=======
- NEW_INS (cfg, ins, temp2, OP_LADD);
->>>>>>> .merge-right.r95529
temp2->sreg1 = ins->inst_basereg;
temp2->sreg2 = temp->dreg;
temp2->dreg = mono_regstate_next_int (cfg->rs);
@@ -2027,11 +2017,7 @@
if (sum_reg == 0)
sum_reg = temp->dreg;
else {
-<<<<<<< .working
NEW_INS (cfg, temp2,
OP_LADD);
-=======
- NEW_INS (cfg, ins,
temp2, OP_LADD);
->>>>>>> .merge-right.r95529
temp2->dreg =
mono_regstate_next_int (cfg->rs);
temp2->sreg1 = sum_reg;
temp2->sreg2 =
temp->dreg;
@@ -2044,13 +2030,8 @@
}
break;
}
-<<<<<<< .working
case OP_LCONV_TO_OVF_U4:
NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
-=======
- case OP_LCONV_TO_OVF_U4:
- NEW_INS (cfg, ins, temp, OP_IA64_CMP4_LT);
->>>>>>> .merge-right.r95529
temp->sreg1 = ins->sreg1;
temp->sreg2 = IA64_R0;
@@ -2059,13 +2040,8 @@
ins->opcode = OP_MOVE;
break;
-<<<<<<< .working
case OP_LCONV_TO_OVF_I4_UN:
NEW_INS (cfg, temp, OP_ICONST);
-=======
- case OP_LCONV_TO_OVF_I4_UN:
- NEW_INS (cfg, ins, temp, OP_ICONST);
->>>>>>> .merge-right.r95529
temp->inst_c0 = 0x7fffffff;
temp->dreg = mono_regstate_next_int (cfg->rs);
@@ -2467,16 +2443,9 @@
ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG,
ins->sreg2);
break;
- case OP_LSHL:
- ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
- break;
case OP_LSHR_UN:
ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
- case OP_LSUB:
- case OP_ISUB:
- ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
- break;
case OP_IADDCC:
/* p6 and p7 is set if there is signed/unsigned
overflow */
@@ -2976,23 +2945,11 @@
ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
break;
case OP_ICONV_TO_R8:
- ia64_setf_sig (code, ins->dreg, ins->sreg1);
- ia64_fcvt_xf (code, ins->dreg, ins->dreg);
- ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
- break;
- /* FIXME: Difference with OP_ICONV_TO_R8 ? */
- case OP_ICONV_TO_R8:
case OP_LCONV_TO_R8:
ia64_setf_sig (code, ins->dreg, ins->sreg1);
ia64_fcvt_xf (code, ins->dreg, ins->dreg);
ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
break;
- case OP_LCONV_TO_R4:
- /* FIXME: Difference with OP_ICONV_TO_R4 ? */
- ia64_setf_sig (code, ins->dreg, ins->sreg1);
- ia64_fcvt_xf (code, ins->dreg, ins->dreg);
- ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
- break;
case OP_FCONV_TO_R4:
ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
break;
@@ -3102,6 +3059,7 @@
if (ia64_is_imm14 (ins->inst_offset))
ia64_adds_imm (code, IA64_R8, ins->inst_offset,
ins->sreg1);
else {
+ printf ("A: %lx\n", ins->inst_offset);
ia64_movl (code, GP_SCRATCH_REG,
ins->inst_offset);
ia64_add (code, IA64_R8, GP_SCRATCH_REG,
ins->sreg1);
}
@@ -3386,8 +3344,15 @@
/* Signal to endfilter that we are called by
call_filter */
ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
- /* Save the return address */
- ia64_adds_imm (code, GP_SCRATCH_REG2,
spvar->inst_offset, cfg->frame_reg);
+ /* Branch target: */
+ if (ia64_is_imm14 (spvar->inst_offset))
+ ia64_adds_imm (code, GP_SCRATCH_REG2,
spvar->inst_offset, cfg->frame_reg);
+ else {
+ ia64_movl (code, GP_SCRATCH_REG2,
spvar->inst_offset);
+ ia64_add (code, GP_SCRATCH_REG2,
cfg->frame_reg, GP_SCRATCH_REG2);
+ }
+
+ /* Save the return address */
ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG,
0);
ia64_codegen_set_one_ins_per_bundle (code, FALSE);
@@ -3399,7 +3364,12 @@
MonoInst *spvar = mono_find_spvar_for_region (cfg,
bb->region);
/* Load the return address */
- ia64_adds_imm (code, GP_SCRATCH_REG,
spvar->inst_offset, cfg->frame_reg);
+ if (ia64_is_imm14 (spvar->inst_offset)) {
+ ia64_adds_imm (code, GP_SCRATCH_REG,
spvar->inst_offset, cfg->frame_reg);
+ } else {
+ ia64_movl (code, GP_SCRATCH_REG,
spvar->inst_offset);
+ ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg,
GP_SCRATCH_REG);
+ }
ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
/* Test caller */
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-ops.h
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-ops.h 2008-02-15
11:50:15 UTC (rev 95733)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-ops.h 2008-02-15
11:52:35 UTC (rev 95734)
@@ -22,6 +22,7 @@
MINI_OP(OP_OUTARG, "outarg", NONE, NONE, NONE)
MINI_OP(OP_OUTARG_REG, "outarg_reg", NONE, NONE, NONE)
MINI_OP(OP_OUTARG_FREG, "outarg_freg", NONE, NONE, NONE)
+MINI_OP(OP_OUTARG_FREG_R4, "outarg_freg_r4", NONE, NONE, NONE)
MINI_OP(OP_OUTARG_IMM, "outarg_imm", NONE, NONE, NONE)
MINI_OP(OP_OUTARG_R4, "outarg_r4", NONE, NONE, NONE)
MINI_OP(OP_OUTARG_R8, "outarg_r8", NONE, NONE, NONE)
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